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    SELF-REPAIR AND ENHANCEMENT OF NANOSTRUCTURES BY LIQUIFICATION UNDER GUIDING CONDITIONS
    284.
    发明申请
    SELF-REPAIR AND ENHANCEMENT OF NANOSTRUCTURES BY LIQUIFICATION UNDER GUIDING CONDITIONS 审中-公开
    根据指导条件通过液化自我修复和增强纳米结构

    公开(公告)号：WO2006128102A2

    公开(公告)日：2006-11-30

    申请号：PCT/US2006/020686

    申请日：2006-05-29

    Applicant: PRINCETON UNIVERSITY ,  CHOU, Stephen Y. ,  XIA, Qiangfei

    Inventor： CHOU, Stephen Y. ,  XIA, Qiangfei

    IPC: H01L29/24

    CPC classification number: B81C1/00111 ,  B81C1/00634 ,  B81C2201/0149 ,  B82Y30/00 ,  H01L21/76892 ,  H01L21/76894 ,  Y10S977/888 ,  Y10S977/90

    Abstract: In accordance with the invention, the structure of a patterned nanoscale or near nanoscale device ("nanostructure") is repaired and/or enhanced by liquifying the patterned device in the presence of appropriate guiding conditions for a period of time and then permitting the device to solidify. Advantageous guiding conditions include adjacent spaced apart or contacting surfaces to control surface structure and preserve vertically. Unconstrained boundaries to permit smoothing of edge roughness. In an advantageous embodiment, a flat planar surface is disposed overlying a patterned nanostructure surface and the surface is liquified by a high intensity light source to repair or enhance the nanoscale features.

    Abstract translation: 根据本发明，通过在适当的引导条件存在一段时间的情况下液化图案化的器件来修复和/或增强图案化纳米尺度或近似纳米级器件（“纳米结构”）的结构，然后允许器件 固化。 有利的引导条件包括相邻的间隔开或接触表面，以控制表面结构并垂直保留。 无约束边界，允许平滑边缘粗糙度。 在有利的实施例中，平坦的平坦表面设置在图案化的纳米结构表面上，并且表面被高强度光源液化以修复或增强纳米尺度特征。

    A METHOD OF FORMING NANO-PATTERNS ON A SUBSTRATE
    286.
    发明申请
    A METHOD OF FORMING NANO-PATTERNS ON A SUBSTRATE 审中-公开
    在衬底上形成纳米图案的方法

    公开(公告)号：WO2018044240A1

    公开(公告)日：2018-03-08

    申请号：PCT/SG2017/050440

    申请日：2017-09-05

    Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

    Inventor： YANG, Kwang Wei Joel ,  DONG, Zhaogang ,  PANIAGUA-DOMINGUEZ, Ramón ,  KUZNETSOV, Arseniy ,  YU, Yefeng

    IPC: B82Y40/00 ,  G02B1/118

    CPC classification number: G02B1/118 ,  B81C1/00031 ,  B81C1/00388 ,  B81C2201/0149 ,  B82Y40/00 ,  G02B1/115 ,  G03F7/0002 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/31144

    Abstract: This application relates to a method of forming nano-patterns on a substrate comprising the step of forming a plurality of nanostructures on a dielectric substrate, wherein the nanostructures are dimensioned or spaced apart from each other by a scaling factor of the dielectric substrate with reference to a silicon substrate. There is also provided a method of forming a nano-patterned substrate comprising the step of forming a plurality of nanostructures on a dielectric substrate, wherein said dielectric substrate comprises an anti-reflectance layer disposed on a base substrate. There is also provided a method of forming a nano-patterned substrate comprising the steps of forming a plurality of nanostructures on a dielectric substrate, wherein the dielectric substrate comprises an anti-reflectance layer disposed on a base substrate, wherein the nanostructures comprise a dielectric material, and wherein the nanostructures are dimensioned or spaced apart from each other by a scaling factor of the dielectric material with reference to a silicon substrate.

    Abstract translation: 本申请涉及在衬底上形成纳米图案的方法，包括在介电衬底上形成多个纳米结构的步骤，其中纳米结构通过刻度尺彼此间隔开 参考硅衬底的介电衬底的因子。 还提供了一种形成纳米图案化基板的方法，其包括在介电基板上形成多个纳米结构的步骤，其中所述介电基板包括设置在基板上的抗反射层。 还提供了一种形成纳米图案化基板的方法，其包括以下步骤：在介电基板上形成多个纳米结构，其中所述介电基板包括设置在基板上的抗反射层，其中所述纳米结构包含介电材料 并且其中所述纳米结构相对于硅衬底通过所述介电材料的比例因子彼此成尺寸或间隔开。

    SPIN-ON LAYER FOR DIRECTED SELF ASSEMBLY WITH TUNABLE NEUTRALITY
    288.
    发明申请
    SPIN-ON LAYER FOR DIRECTED SELF ASSEMBLY WITH TUNABLE NEUTRALITY 审中-公开
    用于具有可逆中性的方向自组装的旋转层

    公开(公告)号：WO2016149257A1

    公开(公告)日：2016-09-22

    申请号：PCT/US2016/022450

    申请日：2016-03-15

    Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON U.S. HOLDINGS, INC.

    Inventor： SMITH, Jeffrey

    IPC: H01L21/027

    CPC classification number: G03F7/11 ,  B81C2201/0149 ,  B82Y30/00 ,  C08L53/00 ,  C09D153/00 ,  G03F7/0002 ,  G03F7/002 ,  G03F7/004 ,  G03F7/16 ,  G03F7/165 ,  G03F7/2059 ,  G03F7/26 ,  G03F7/265 ,  G03F7/40 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31058

    Abstract: Techniques disclosed herein include methods for creating a directed self-assembly tunable neutral layer that works with multiple different block copolymer materials. Techniques herein can include depositing a neutral layer and then post-processing this neutral layer to tune its characteristics so that the neutral layer is compatible with a particular block copolymer scheme or schemes. Post-processing herein of such a neutral layer can modify a ratio of pi and sigma bonds in a given carbon film or other film to approximate a given self-assembly film that will be deposited on this neutral layer. Accordingly, a generic or single material can be used for a neutral layer and modified to match a given block copolymer to be deposited.

    Abstract translation: 本文公开的技术包括用于产生与多种不同嵌段共聚物材料一起使用的定向自组装可调谐中性层的方法。 本文的技术可以包括沉积中性层，然后后处理该中性层以调节其特性，使得中性层与特定的嵌段共聚物方案或方案相容。 这种中性层的后处理可以改变给定碳膜或其它膜中的π和σ键的比例，以近似将沉积在该中性层上的给定自组装膜。 因此，通用或单一材料可以用于中性层并经修饰以匹配待沉积的给定嵌段共聚物。

    DEFECT REDUCTION METHODS AND COMPOSITION FOR VIA FORMATION IN DIRECTED SELF-ASSEMBLY PATTERNING
    289.
    发明申请
    DEFECT REDUCTION METHODS AND COMPOSITION FOR VIA FORMATION IN DIRECTED SELF-ASSEMBLY PATTERNING 审中-公开
    通过指导自组装方式形成的缺陷减少方法和组成

    公开(公告)号：WO2016066691A1

    公开(公告)日：2016-05-06

    申请号：PCT/EP2015/074993

    申请日：2015-10-28

    Applicant: AZ ELECTRONIC MATERIALS (LUXEMBOURG) S.À.R.L.

    Inventor： HONG, SungEun ,  MATSUMOTO, Naomi ,  AKIYAMA, Yasushi ,  KUROSAWA, Kazunori ,  MIYAZAKI, Shinji ,  LIN, Guanyang

    IPC: B81C1/00

    CPC classification number: C09D153/00 ,  B81C1/00031 ,  B81C1/00396 ,  B81C2201/0149 ,  H01J37/32009 ,  H01L21/3081

    Abstract: The present invention relates to a two novel processes, "Dual Coating Process and Single Coating Process," for forming an array of via's by employing a graphoepitaxy approach, where an array of pillars the surface of the pillars has been modified by the formation of a hydrophobic poly(vinyl aryl) brush at the surface of the pillars. The present invention also relates to a composition comprising a poly(vinyl aryl) hydrophopic polymer brush precursor terminated at one chain end with a reactive functional group, a diblock copolymer comprising an etch resistant hydrophobic block and a highly etchable hydrophilic block, a thermal acid generator and a solvent.

    Abstract translation: 本发明涉及两种新型工艺：“双重涂布工艺和单一涂覆工艺”，用于通过采用石墨刻蚀方法形成通孔阵列，其中支柱的表面阵列已经通过形成 疏水性聚（乙烯基芳基）刷在柱子的表面。 本发明还涉及一种组合物，其包含在一个末端用反应性官能团封端的聚（乙烯基芳基）水薰衣草聚合物刷子前体，包含耐蚀刻疏水嵌段的二嵌段共聚物和高度可蚀刻的亲水性嵌段，热酸产生剂 和溶剂。

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