公开(公告)号：FR2884048A1

公开(公告)日：2006-10-06

申请号：FR0503207

申请日：2005-04-01

Applicant: 3D PLUS SA SA

Inventor： VAL CHRISTIAN

IPC: H01L23/498 ,  H01L25/16 ,  H05K3/34

Abstract: L'invention concerne un module électronique (100) comprenant un empilement de n boîtiers (10, 10a, 10b) d'épaisseur E prédéterminée, pourvus sur une surface inférieure de billes de connexion (12) d'épaisseur eb prédéterminée reliées à un circuit imprimé (20, 20a, 20b) d'interconnexion du boîtier. Le circuit imprimé est disposé sur la surface inférieure du boîtier au niveau des billes, présente des percements métallisés (23) dans lesquels sont situées les billes (12) et auxquels elles sont connectées, et a une épaisseur eci inférieure à eb, de manière à obtenir un module d'épaisseur totale ne dépassant pas E x n.

公开(公告)号：FR2857157A1

公开(公告)日：2005-01-07

申请号：FR0307977

申请日：2003-07-01

Applicant: 3D PLUS SA

Inventor： VAL CHRISTIAN ,  LIGNIER OLIVIER

IPC: H01L21/60 ,  H01L21/68 ,  H01L21/98 ,  H01L23/538 ,  H01L25/16 ,  H01L21/58 ,  H01L23/52

Abstract: A method for interconnecting active and passive components in two or three dimensions, and the resulting thin heterogeneous components. The method comprises: positioning and fixing (11) at least one active component and one passive component on a flat support (23), the terminals being in contact with the support, depositing (12) a polymer layer (24) on all of the support and the components, removing the support (14), redistributing the terminals (15) between the components and/or toward the periphery by metal conductors (26) arranged in a predetermined layout, making it possible to obtain a heterogeneous reconstituted structure, heterogeneously thinning (16) the structure by nonselective surface treatment of the polymer layer and at least one passive component (22).

公开(公告)号：FR2895568A1

公开(公告)日：2007-06-29

申请号：FR0513217

申请日：2005-12-23

Applicant: 3D PLUS SA SA

Inventor： VAL CHRISTIAN

IPC: H01L25/065

Abstract: L'invention concerne la fabrication collective de n modules 3D. Elle comprend une étape de fabrication d'un lot de n tranches i sur une même plaque, cette étape étant répétée K fois, puis une étape d'empilement des K plaques, de formation de trous métallisés dans l'épaisseur de l'empilement et destinés à la connexion des tranches entre elles, puis de découpe de l'empilement pour obtenir les n modules 3D.La plaque 10 qui comprend du silicium est recouverte sur une face 11 d'une couche électriquement isolante formant le substrat isolant. Cette face présente des rainures 20 qui délimitent n motifs géométriques, munis d'un composant électronique 1 connecté à des plots de connexion électrique 2' disposés sur ladite face.Après l'empilement, des trous sont percés perpendiculairement aux faces des plaques à l'aplomb des rainures ; la dimension des trous est inférieure à celle des rainures, de manière à ce que le silicium de chaque tranche 10 soit isolé de la paroi du trou par de la résine.C2) métalliser la paroi des trous,D2) découper l'empilement selon les rainures en vue d'obtenir les n modules électroniques

公开(公告)号：FR2832136A1

公开(公告)日：2003-05-16

申请号：FR0114543

申请日：2001-11-09

Applicant: 3D PLUS SA

Inventor： VAL CHRISTIAN

IPC: G02B6/42 ,  B81B7/00 ,  B81B7/02 ,  H01L23/10 ,  H01L23/31 ,  H01L23/34 ,  H01L31/0203 ,  H01L31/024 ,  B65D85/00 ,  B65B31/00

Abstract: The invention relates to a device that is used for the hermetic encapsulation of a component that must protected against all stresses. The aforementioned component (5) is fixed to a substrate (15) having a temperature control element (17) glued (16) to the other face thereof. Said assembly is disposed in a case comprising two parts (11, 12) which are assembled by means of gluing (13), with a passage for optical links (6) and electrical connections (18, 142). Said component is supported by elements (19) which project out from one part (11) of the case. A unit (14) is glued to the other part (12) of the case, said unit comprising three-dimensional interconnections which form the temperature regulation electronics. The aforementioned unit, case (11, 12) and a minimum length (L) of the links and connections are encased in a mineral protective layer (4'). In particular, the invention can be used for optoelectronic components and MEMS components.

公开(公告)号：FR2802706B1

公开(公告)日：2002-03-01

申请号：FR9915838

申请日：1999-12-15

Applicant: 3D PLUS SA

Inventor： VAL CHRISTIAN

IPC: H05K3/28 ,  H01L21/98 ,  H01L23/522 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/04 ,  H05K3/40 ,  H05K3/46 ,  H01L23/52 ,  H01L21/50 ,  H01L25/00

Abstract: 3D interconnection method of casings or circuits containing electronic components and connecting conductors, where the casings or circuits are stacked in the form of a block (3') by encapsulation by an insulator, involves: (a) the cutting of block by leaving the extremities of conductors (21) indented with respect to corresponding faces (302); (b) the cutting of grooves (40,41) in the faces and perpendicular ones; (c) the metallization of block and the grooves; (d) polishing the faces to remove metallization; (e) encapsulation by resin (303); and (f) metallization of block to ensure shielding (304). The method also includes, in a variant of invention, for supplying power to circuits, a Bus bar, and at step (b) at least one of the grooves cuts into the extremities of two adjacent conductors; the method includes an additional step, that is (g) the cutting of second grooves in the bottom of first grooves in full length, implemented between steps (c) and (e). The width of second grooves is less than that of first grooves. The cutting of grooves is done by sawing, or by use of laser. In another variant of invention, the method comprises an additional step, that is (h) the introduction of a capacitor by bonding plates to lateral faces of groove by a conducting adhesive, which is implemented before step (e). An electronic device with interconnections in three dimensions comprising casings or circuits with connecting conductors and encapsulated to form a block, is made with grooves and metallization according to the method. The metallization is interrupted in full length of second grooves.

公开(公告)号：FR2802706A1

公开(公告)日：2001-06-22

申请号：FR9915838

申请日：1999-12-15

Applicant: 3D PLUS SA

Inventor： VAL CHRISTIAN

IPC: H05K3/28 ,  H01L21/98 ,  H01L23/522 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/04 ,  H05K3/40 ,  H05K3/46 ,  H01L23/52 ,  H01L21/50 ,  H01L25/00

Abstract: 3D interconnection method of casings or circuits containing electronic components and connecting conductors, where the casings or circuits are stacked in the form of a block (3') by encapsulation by an insulator, involves: (a) the cutting of block by leaving the extremities of conductors (21) indented with respect to corresponding faces (302); (b) the cutting of grooves (40,41) in the faces and perpendicular ones; (c) the metallization of block and the grooves; (d) polishing the faces to remove metallization; (e) encapsulation by resin (303); and (f) metallization of block to ensure shielding (304). The method also includes, in a variant of invention, for supplying power to circuits, a Bus bar, and at step (b) at least one of the grooves cuts into the extremities of two adjacent conductors; the method includes an additional step, that is (g) the cutting of second grooves in the bottom of first grooves in full length, implemented between steps (c) and (e). The width of second grooves is less than that of first grooves. The cutting of grooves is done by sawing, or by use of laser. In another variant of invention, the method comprises an additional step, that is (h) the introduction of a capacitor by bonding plates to lateral faces of groove by a conducting adhesive, which is implemented before step (e). An electronic device with interconnections in three dimensions comprising casings or circuits with connecting conductors and encapsulated to form a block, is made with grooves and metallization according to the method. The metallization is interrupted in full length of second grooves.