公开(公告)号：WO0173812A3

公开(公告)日：2002-03-07

申请号：PCT/US0140285

申请日：2001-03-13

Applicant: LAM RES CORP ,  BAILEY ANDREW D III

Inventor： BAILEY ANDREW D III

IPC: H01J37/32

CPC classification number: H01J37/321 ,  H01J37/32623 ,  H01J37/32688

Abstract: A plasma confinement arrangement for controlling the volume of a plasma while processing a substrate inside a process chamber includes a chamber within which a plasma is both ignited and sustained for processing. The chamber is defined at least in part by a wall and further includes a plasma confinement arrangement. The plasma confinement arrangement includes a magnetic array disposed inside of the chamber. The magnetic array has a plurality of magnetic elements that are disposed around a plasma region within the process chamber.The magnetic field establishes a containment field (a type of "magnetic wall") within the chamber. The containment field can be shifted in a preselected manner to improve operation of the substrate processing system and to reduce the damage and/or cleaning problems caused by the plasma's interaction with other elements of the processing system. Shifting of the containment field can be accomplished by moving magnetic elements in the magnetic array.

Abstract translation: 用于在处理处理室内处理衬底的同时控制等离子体的体积的等离子体限制装置包括其中等离子体都被点燃并持续进行处理的室。 腔室至少部分地由壁限定，并且还包括等离子体限制装置。 等离子体限制装置包括设置在腔室内部的磁阵列。 磁性阵列具有多个磁性元件，其设置在处理室内的等离子体区域周围。磁场在腔室内建立了容纳场（一种“磁性壁”）。 容纳场可以以预先选择的方式移动以改善基板处理系统的操作并且减少由等离子体与处理系统的其它元件的相互作用引起的损坏和/或清洁问题。 容纳场的移动可以通过移动磁性阵列中的磁性元件来实现。

公开(公告)号：WO2012018449A3

公开(公告)日：2012-04-12

申请号：PCT/US2011041524

申请日：2011-06-22

Applicant: LAM RES CORP ,  DHINDSA RAJINDER ,  MARAKHATNOV ALEXEI ,  BAILEY ANDREW D III

Inventor： DHINDSA RAJINDER ,  MARAKHATNOV ALEXEI ,  BAILEY ANDREW D III

IPC: H01L21/205

CPC classification number: H01J37/32449 ,  H01J37/32091 ,  H01J37/32697 ,  H01J37/32715 ,  H01J37/32834 ,  H01L21/67069 ,  H01L21/67259 ,  H01L21/6831 ,  H01L22/26

Abstract: A semiconductor wafer processing apparatus includes a first electrode exposed to a first plasma generation volume, a second electrode exposed to a second plasma generation volume, and a gas distribution unit disposed between the first and second plasma generation volumes. The first electrode is defined to transmit radio frequency (RF) power to the first plasma generation volume, and distribute a first plasma process gas to the first plasma generation volume. The second electrode is defined to transmit RF power to the second plasma generation volume, and hold a substrate in exposure to the second plasma generation volume. The gas distribution unit includes an arrangement of through-holes defined to fluidly connect the first plasma generation volume to the second plasma generation volume. The gas distribution unit also includes an arrangement of gas supply ports defined to distribute a second plasma process gas to the second plasma generation volume.

Abstract translation: 半导体晶片处理装置包括暴露于第一等离子体产生体积的第一电极，暴露于第二等离子体产生体积的第二电极和设置在第一和第二等离子体产生体积之间的气体分配单元。 第一电极被定义为将射频（RF）功率传送到第一等离子体产生体积，并且将第一等离子体处理气体分配到第一等离子体产生体积。 第二电极被定义为将RF功率传送到第二等离子体产生体积，并且保持衬底暴露于第二等离子体产生体积。 气体分配单元包括限定为将第一等离子体产生体积流体连接到第二等离子体产生体积的通孔的布置。 气体分配单元还包括被定义为将第二等离子体处理气体分配到第二等离子体产生体积的气体供给端口的布置。

公开(公告)号：WO2009042997A3

公开(公告)日：2009-07-16

申请号：PCT/US2008078110

申请日：2008-09-29

Applicant: LAM RES CORP ,  BAILEY ANDREW D III

Inventor： BAILEY ANDREW D III

IPC: H01L21/68 ,  H01L21/205 ,  H01L21/3065

CPC classification number: H01L22/12 ,  G01B21/08 ,  G01B21/20 ,  G01B21/30 ,  H01L22/20

Abstract: An arrangement for quantifying a wafer bow. The arrangement is positioned within a plasma processing system is provided. The arrangement includes a support mechanism for holding a wafer. The arrangement also includes a first set of sensors, which is configured to collect a first set of measurement data for a plurality of data points on the wafer. The first set of measurement data indicates a minimum gap between the first set of sensors and the wafer. The first set of sensors is positioned in a first location, which is outside of a set of process modules of the plasma processing system.

Abstract translation: 用于量化晶片弓的布置。 该装置位于等离子体处理系统内。 该装置包括用于保持晶片的支撑机构。 该布置还包括第一组传感器，其被配置为收集晶片上的多个数据点的第一组测量数据。 第一组测量数据表示第一组传感器和晶片之间的最小间隙。 第一组传感器位于第一位置，其位于等离子体处理系统的一组处理模块之外。

公开(公告)号：WO2009042997A2

公开(公告)日：2009-04-02

申请号：PCT/US2008078110

申请日：2008-09-29

Applicant: LAM RES CORP ,  BAILEY ANDREW D III

Inventor： BAILEY ANDREW D III

IPC: H01L21/68 ,  H01L21/20 ,  H01L21/30

CPC classification number: H01L22/12 ,  G01B21/08 ,  G01B21/20 ,  G01B21/30 ,  H01L22/20

Abstract: An arrangement for quantifying a wafer bow. The arrangement is positioned within a plasma processing system is provided. The arrangement includes a support mechanism for holding a wafer. The arrangement also includes a first set of sensors, which is configured to collect a first set of measurement data for a plurality of data points on the wafer. The first set of measurement data indicates a minimum gap between the first set of sensors and the wafer. The first set of sensors is positioned in a first location, which is outside of a set of process modules of the plasma processing system.

公开(公告)号：WO2008156542A1

公开(公告)日：2008-12-24

申请号：PCT/US2008/006551

申请日：2008-05-20

Applicant: LAM RESEARCH CORPORATION ,  BAILEY, Andrew, D., III ,  KIM, Yunsang

Inventor： BAILEY, Andrew, D., III ,  KIM, Yunsang

IPC: H01L21/3065

CPC classification number: H01J37/32385 ,  H01J37/321 ,  H01J37/32366 ,  H01J37/32706 ,  H01L21/02087 ,  H01L21/67069 ,  H01L21/6715

Abstract: Apparatus and methods protect a central process exclusion region of a substrate during processing of an edge environ region of process performance. Removal of undesired materials is only from the edge environ region while the central device region is protected from damage. Field strengths are configured to protect the central region from charged particles from plasma in a process chamber and to foster removal of the undesired materials from only the edge environ region. A magnetic field is configured with a peak value adjacent to a border between the central and edge environ regions. A strong field gradient extends from the peak radially away from the border and away from the central region to repel the charged particles from the central region. The strength and location of the field are adjustable by axial relative movement of magnet sections, and flux plates are configured to redirect the field for desired protection.

Abstract translation: 装置和方法在处理工艺性能的边缘环境区域期间保护衬底的中心过程排除区域。 去除不需要的材料仅来自边缘环境区域，而中央设备区域被保护免受损坏。 场强被配置为保护中心区域免受处理室中的带电粒子等离子体的影响，并且仅促进从边缘环境区域移除不需要的材料。 磁场配置有与中央和边缘环境区域之间的边界相邻的峰值。 强场梯度从径向远离边界并远离中心区域从峰值延伸，以将带电粒子从中心区域排斥。 磁场的强度和位置可以通过磁体部分的轴向相对运动来调节，并且磁通板被配置为重定向磁场以达到期望的保护。

公开(公告)号：WO2008042580A2

公开(公告)日：2008-04-10

申请号：PCT/US2007078576

申请日：2007-09-14

Applicant: LAM RES CORP ,  CHEN JACK ,  BAILEY ANDREW D III ,  MOORING BEN ,  CAIN STEPHEN J

Inventor： CHEN JACK ,  BAILEY ANDREW D III ,  MOORING BEN ,  CAIN STEPHEN J

IPC: H01L21/66 ,  G06F19/00

CPC classification number: G05B19/41875 ,  G05B2219/37398 ,  G05B2219/45031 ,  G05B2219/50057 ,  Y02P90/22

Abstract: A method for calculating a process center for a chuck in a processing chamber is provided. The method includes generating pre-processing and post-processing measurement data points, which is perform by measuring thickness of a film substrate at a set of orientations and a set of distances from a geometric center of the substrate. The method also includes comparing the pre-processing and post-processing measurement data points to calculate a set of etch depth numbers. The method further includes generating etch profiles for the set of orientations. The method yet also includes extrapolating a set of radiuses, which is associated with a first etch depth, from the etch profiles. The method yet further includes generating an off-centered plot, which is a graphical representation of the set of radiuses versus the set of orientations. The method more over includes calculating the process center by applying a curve-fitting equation to the off-centered plot.

Abstract translation: 提供了一种用于计算处理室中的卡盘的处理中心的方法。 该方法包括产生预处理和后处理测量数据点，其通过以一组取向和距离基板的几何中心的一组距离测量薄膜基板的厚度来执行。 该方法还包括比较预处理和后处理测量数据点以计算一组蚀刻深度数。 该方法还包括产生该组取向的蚀刻轮廓。 该方法还包括从蚀刻轮廓推断与第一蚀刻深度相关联的一组半径。 该方法还包括生成偏心图，其是该组半径与该组取向的图形表示。 更多的方法包括通过对偏心图应用曲线拟合方程来计算过程中心。

公开(公告)号：WO2007038256A2

公开(公告)日：2007-04-05

申请号：PCT/US2006/036959

申请日：2006-09-22

Applicant: LAM RESEARCH CORPORATION ,  YOON, Hyungsuk, Alexander ,  THIE, William ,  DORDI, Yezdi ,  BAILEY, Andrew, D., III

Inventor： YOON, Hyungsuk, Alexander ,  THIE, William ,  DORDI, Yezdi ,  BAILEY, Andrew, D., III

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/31116 ,  H01L21/02063 ,  H01L21/67069 ,  H05H1/24 ,  H05H1/2406 ,  H05H1/48 ,  H05H2001/2418

Abstract: An apparatus generating a plasma for removing metal oxide from a substrate is disclosed. The embodiment includes a powered electrode assembly, including a powered electrode, a first dielectric layer, and a first wire mesh disposed between the powered electrode and the first dielectric layer. The embodiment also includes a grounded electrode assembly disposed opposite the powered electrode assembly so as to form a cavity wherein the plasma is generated, the first wire mesh being shielded from the plasma by the first dielectric layer when the plasma is present in the cavity, the cavity having an outlet at one end for providing the plasma to remove the metal oxide.

Abstract translation: 公开了一种从衬底生成用于去除金属氧化物的等离子体的装置。 该实施例包括动力电极组件，其包括供电电极，第一介电层和设置在电源电极和第一介电层之间的第一丝网。 该实施例还包括与动力电极组件相对设置的接地电极组件，以便形成其中产生等离子体的空腔，当等离子体存在于空腔中时，第一电线网被第一电介质层与等离子体屏蔽， 空腔在一端具有出口，用于提供等离子体以去除金属氧化物。

公开(公告)号：WO2007005211A2

公开(公告)日：2007-01-11

申请号：PCT/US2006/023033

申请日：2006-06-13

Applicant: LAM RESEARCH CORPORATION ,  BAILEY, Andrew, D., III

Inventor： BAILEY, Andrew, D., III

IPC: G01R35/00

CPC classification number: G01B7/105 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of determining a first thickness of a first conductive film formed of a first conductive material on a target substrate is disclosed. The method includes positioning a first eddy current sensor near a set of positions on the target substrate. The method also includes measuring, using the first eddy current sensor, a first set of electrical responses that includes at least one of a first voltage measurement and a first current measurement. The method further includes correcting the set of first electrical responses using a temperature-dependent compensation factor, thereby obtaining a corrected first set of electrical responses, the temperature-dependent compensation factor being obtained from a calibration substrate different from the target substrate, the calibration substrate having a second conductive film formed of a second conductive material that is substantially similar to the first conductive material of the target substrate; and determining the first thickness using the corrected first set of electrical responses.

Abstract translation: 公开了一种确定由目标衬底上的第一导电材料形成的第一导电膜的第一厚度的方法。 该方法包括将第一涡电流传感器定位在目标衬底上的一组位置附近。 该方法还包括使用第一涡流传感器测量包括第一电压测量和第一电流测量中的至少一个的第一组电响应。 所述方法还包括使用温度依赖性补偿因子校正所述一组第一电响应，由此获得校正的第一组电响应，所述温度相关补偿因子从不同于所述目标衬底的校准衬底获得，所述校准衬底 具有由与靶基板的第一导电材料基本相似的第二导电材料形成的第二导电膜; 以及使用所述校正的第一组电响应来确定所述第一厚度。

公开(公告)号：WO2006036893B1

公开(公告)日：2006-06-01

申请号：PCT/US2005034427

申请日：2005-09-23

Applicant: LAM RES CORP ,  BAILEY ANDREW D III ,  YADAV PUNEET

Inventor： BAILEY ANDREW D III ,  YADAV PUNEET

IPC: G06F11/30 ,  G06F15/00 ,  G21C17/00

CPC classification number: H01J37/32935

Abstract: A computer-implemented data presentation technique for presenting a set of expected failure states of system-related constructs pertaining to a plasma processing system is disclosed. The technique includes receiving a set of indicia pertaining to a first system-related construct of said system-related constructs. The technique also includes computing, in accordance with a first sub-method and responsive to said receiving said first set of indicia, a first expected failure state value. The technique further includes computing a first normalized expected failure state value in accordance with a first weight; correlating said first normalized expected failure state value to a first color; and displaying said first color in a cell of an n-dimensional matrix, wherein n is a number greater than 2.

Abstract translation: 公开了用于呈现与等离子体处理系统有关的系统相关构造的一组预期故障状态的计算机实现的数据呈现技术。 该技术包括接收与所述系统相关构造的第一系统相关构造有关的一组标记。 该技术还包括根据第一子方法并响应于所述接收所述第一组标记来计算第一预期故障状态值。 该技术还包括根据第一权重计算第一标准化预期故障状态值; 将所述第一标准化预期故障状态值与第一颜色相关联; 以及在n维矩阵的单元中显示所述第一颜色，其中n是大于2的数。

公开(公告)号：WO2004084267A3

公开(公告)日：2006-02-23

申请号：PCT/US2004007530

申请日：2004-03-10

Applicant: LAM RES CORP ,  LOHOKARE SHRIKANT P ,  BAILEY ANDREW D III ,  HEMKER DAVID ,  COOK JOEL M

Inventor： LOHOKARE SHRIKANT P ,  BAILEY ANDREW D III ,  HEMKER DAVID ,  COOK JOEL M

IPC: H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/32135 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/7684

Abstract: A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate (100). The patterned semiconductor substrate includes a conductive interconnect material (120) filling multiple of features (102, 104,106) in the pattern. The conductive interconnect material having an overburden portion (112). The overburden portion (112) includes a localized non-uniformity (indicated in variations 114, 116, 118). An additional layer (202) is formed an the overburden portion. The additional layer and the overburden portion are planarized. The planarizing process substantially entirely removes the additional layer.

Abstract translation: 用于平坦化图案化半导体衬底的系统和方法包括接收图案化的半导体衬底（100）。 图案化的半导体衬底包括以图案填充多个特征（102,104,106）的导电互连材料（120）。 所述导电互连材料具有覆盖层部分（112）。 覆盖层部分（112）包括局部不均匀性（在变化形式114,116,118中指示）。 附加层（202）形成为上覆层部分。 附加层和覆盖层部分被平坦化。 平坦化工艺基本上完全除去附加层。