公开(公告)号：IL170852A

公开(公告)日：2010-06-30

申请号：IL17085205

申请日：2005-09-13

Applicant: III ANDREW D BAILEY ,  LAM RES CORP ,  LOHOKARE SHRIKANT P ,  HEMKER DAVID ,  COOK JOEL M

Inventor： III ANDREW D BAILEY ,  LOHOKARE SHRIKANT P ,  HEMKER DAVID ,  COOK JOEL M

IPC: B44C1/22 ,  H01L20060101 ,  H01L21/302 ,  H01L21/304 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/4763 ,  H01L21/768 ,  H01L33/00

Abstract: A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion having a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion. The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.

公开(公告)号：IL170851A

公开(公告)日：2010-05-31

申请号：IL17085105

申请日：2005-09-13

Applicant: LAM RES CORP ,  III ANDREW D BAILEY ,  LOHOKARE SHRIKANT P ,  HEMKER DAVID ,  COOK JOEL M

Inventor： III ANDREW D BAILEY ,  LOHOKARE SHRIKANT P ,  HEMKER DAVID ,  COOK JOEL M

IPC: H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768

Abstract: A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion includes a localized non-uniformity. An additional layer is formed on the overburden portion. The additional layer and the overburden portion are planarized. The planarizing process substantially entirely removes the additional layer.

公开(公告)号：WO2004084266A3

公开(公告)日：2005-05-06

申请号：PCT/US2004007527

申请日：2004-03-10

Applicant: LAM RES CORP ,  LOHOKARE SHRIKANT P ,  BAILEY ANDREW D III ,  HEMKER DAVID ,  COOK JOEL M

Inventor： LOHOKARE SHRIKANT P ,  BAILEY ANDREW D III ,  HEMKER DAVID ,  COOK JOEL M

IPC: B44C1/22 ,  H01L20060101 ,  H01L21/302 ,  H01L21/304 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/4763 ,  H01L21/768 ,  H01L33/00 ,  H01L21/4768

CPC classification number: H01L21/7684 ,  H01L21/31116 ,  H01L21/32115 ,  H01L21/32135 ,  H01L21/32136

Abstract: A system and method for planarizing a patterned semiconductor substrate (100) includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate (100) having a conductive interconnect material (120) filling multiple of features in the pattern. The conductive interconnect material has an overburden portion (112). The overburden portion has a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion (120). The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.

Abstract translation: 用于平坦化图案化半导体衬底（100）的系统和方法包括接收图案化的半导体衬底。 图案化半导体衬底（100）具有填充图案中的多个特征的导电互连材料（120）。 导电互连材料具有覆盖层部分（112）。 覆盖层部分具有局部不均匀性。 去除覆盖层部分的主体部分以平坦化上覆层部分（120）。 映射基本上局部平坦化的覆盖层部分以确定全局不均匀性。 基本上局部平坦化的覆盖层部分被蚀刻以基本上去除全局不均匀性。

公开(公告)号：WO1998014636A1

公开(公告)日：1998-04-09

申请号：PCT/US1997017663

申请日：1997-09-30

Applicant: LAM RESEARCH CORPORATION ,  KENNEDY, William, S. ,  WICKER, Thomas, E. ,  MARASCHIN, Robert, A. ,  COOK, Joel, M. ,  SCHOEPP, Alan, M.

Inventor： LAM RESEARCH CORPORATION

IPC: C23C16/44

CPC classification number: C23C16/45521 ,  C23C16/458 ,  H01J37/321 ,  H01J2237/022 ,  Y10S156/915

Abstract: In a plasma processing system for processing substrates such as semiconductor wafers, deposition of polymer in an area (30) between a focus ring (16) and an electrostatic chuck (14) in a plasma processing chamber (10) is achieved by providing a clearance gas in a gap between the chuck and the focus ring. A series of channels delivers the clearance gas to the annular gap between the outer surface of the substrate support and the inner surface of the focus ring surrounding the substrate support. The clearance gas supplied to the annular gap is preferably a gas such as helium which will not affect the wafer processing operation. In the case of plasma etching, the clearance gas is supplied at a flow rate which is sufficient to block the migration of process gas and volatile by products thereof into the annular gap without adversely affecting edge etch performance.

Abstract translation: 在用于处理诸如半导体晶片的衬底的等离子体处理系统中，通过提供等离子体处理室（10）中的聚焦环（16）和静电吸盘（14）之间的区域（30）中的聚合物的沉积， 在卡盘和聚焦环之间的间隙中的气体。 一系列通道将间隙气体传送到衬底支撑件的外表面和围绕衬底支撑件的聚焦环的内表面之间的环形间隙。 提供给环形间隙的间隙气体优选为不影响晶片加工操作的诸如氦气等气体。 在等离子体蚀刻的情况下，间隙气体以足以阻止工艺气体的迁移并由其产物挥发到环形间隙中的流量提供，而不会不利地影响边缘蚀刻性能。

公开(公告)号：WO1997046730A1

公开(公告)日：1997-12-11

申请号：PCT/US1997009031

申请日：1997-06-02

Applicant: LAM RESEARCH CORPORATION ,  WICKER, Thomas, E. ,  COOK, Joel, M. ,  MARASCHIN, Robert, A. ,  KENNEDY, William, S. ,  BENJAMIN, Neil

Inventor： LAM RESEARCH CORPORATION

IPC: C23C16/50

CPC classification number: C23C16/45565 ,  C23C16/45572 ,  C23C16/507 ,  H01J37/321 ,  H01J37/32522

Abstract: A plasma processing chamber (10) includes a substrate holder (12) and a dielectric member such as a dielectric window (20) or gas distribution plate having an interior surface facing the substrate holder, the interior surface being maintained below a threshold temperature to minimize process drift during processing of substrates. The chamber can include an antenna (18) which inductively couples RF energy through the dielectric member to energize process gas into a plasma state. The antenna can include a channel (24) through which a temperature controlling fluid, which has been cooled by a closed circuit temperature controller, is passed. The control of the temperature of the interior surface minimizes process drift and degradation of the quality of the processed substrates during sequential bath processing of substrates such as during oxide etching of semiconductor wafers.

Abstract translation: 等离子体处理室（10）包括衬底保持器（12）和电介质构件，例如电介质窗（20）或具有面向衬底保持器的内表面的气体分配板，内表面保持在阈值温度以下以最小化 处理衬底时的工艺漂移。 腔室可以包括天线（18），其通过电介质构件感应耦合RF能量，以将处理气体激励成等离子体状态。 天线可以包括通道（24），已经通过闭路温度控制器冷却的温度控制流体通过该通道。 内部表面的温度的控制使得在衬底的顺序浴处理期间（例如在半导体晶片的氧化物蚀刻期间）处理衬底的工艺漂移和质量降低最小化。

公开(公告)号：WO2004084266A2

公开(公告)日：2004-09-30

申请号：PCT/US2004/007527

申请日：2004-03-10

Applicant: LAM RESEARCH CORPORATION ,  LOHOKARE, Shrikant, P. ,  BAILEY, Andrew, D., III ,  HEMKER, David ,  COOK, Joel, M.

Inventor： LOHOKARE, Shrikant, P. ,  BAILEY, Andrew, D., III ,  HEMKER, David ,  COOK, Joel, M.

IPC: H01L

CPC classification number: H01L21/7684 ,  H01L21/31116 ,  H01L21/32115 ,  H01L21/32135 ,  H01L21/32136

Abstract: A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion having a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion. The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.

Abstract translation: 用于平坦化图案化半导体衬底的系统和方法包括接收图案化的半导体衬底。 图案化半导体衬底具有填充图案中的多个特征的导电互连材料。 导电互连材料具有覆盖层部分。 覆盖层部分具有局部不均匀性。 去除覆盖层部分的大部分以平坦化上覆层部分。 映射基本上局部平坦化的覆盖层部分以确定全局不均匀性。 基本上局部平坦化的覆盖层部分被蚀刻以基本上去除全局不均匀性。

公开(公告)号：WO2004084267A3

公开(公告)日：2006-02-23

申请号：PCT/US2004007530

申请日：2004-03-10

Applicant: LAM RES CORP ,  LOHOKARE SHRIKANT P ,  BAILEY ANDREW D III ,  HEMKER DAVID ,  COOK JOEL M

Inventor： LOHOKARE SHRIKANT P ,  BAILEY ANDREW D III ,  HEMKER DAVID ,  COOK JOEL M

IPC: H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/32135 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/7684

Abstract: A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate (100). The patterned semiconductor substrate includes a conductive interconnect material (120) filling multiple of features (102, 104,106) in the pattern. The conductive interconnect material having an overburden portion (112). The overburden portion (112) includes a localized non-uniformity (indicated in variations 114, 116, 118). An additional layer (202) is formed an the overburden portion. The additional layer and the overburden portion are planarized. The planarizing process substantially entirely removes the additional layer.

Abstract translation: 用于平坦化图案化半导体衬底的系统和方法包括接收图案化的半导体衬底（100）。 图案化的半导体衬底包括以图案填充多个特征（102,104,106）的导电互连材料（120）。 所述导电互连材料具有覆盖层部分（112）。 覆盖层部分（112）包括局部不均匀性（在变化形式114,116,118中指示）。 附加层（202）形成为上覆层部分。 附加层和覆盖层部分被平坦化。 平坦化工艺基本上完全除去附加层。

公开(公告)号：WO2004084267A2

公开(公告)日：2004-09-30

申请号：PCT/US2004/007530

申请日：2004-03-10

Applicant: LAM RESEARCH CORPORATION ,  LOHOKARE, Shrikant, P. ,  BAILEY, Andrew, D., III ,  HEMKER, David ,  COOK, Joel, M.

Inventor： LOHOKARE, Shrikant, P. ,  BAILEY, Andrew, D., III ,  HEMKER, David ,  COOK, Joel, M.

IPC: H01L

CPC classification number: H01L21/32135 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/7684

Abstract: A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion includes a localized non-uniformity. An additional layer is formed an the overburden portion. The additional layer and the overburden portion are planarized. The planarizing process substantially entirely removes the additional layer.

Abstract translation: 用于平坦化图案化半导体衬底的系统和方法包括接收图案化的半导体衬底。 图案化半导体衬底具有填充图案中的多个特征的导电互连材料。 导电互连材料具有覆盖层部分。 覆盖层部分包括局部不均匀性。 形成上覆层部分的附加层。 附加层和覆盖层部分被平坦化。 平坦化工艺基本上完全除去附加层。