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21.
公开(公告)号:WO2008011210A1
公开(公告)日:2008-01-24
申请号:PCT/US2007/067916
申请日:2007-05-01
Applicant: FREESCALE SEMICONDUCTOR INC. , CHUNG, Young Sir , BAIRD, Robert W.
Inventor: CHUNG, Young Sir , BAIRD, Robert W.
IPC: H01L21/02
CPC classification number: H01L29/0657 , H01L21/84 , H01L23/3677 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
Abstract: Structure (40, 61-13, 61-15, 61-18, 61-19) and method (60-5... 60-19, 100, 200) are provided for a semiconductor device (40, 61-13, 61-15, 61-18, 61-19) with under-filled heat extractor(s) (46, 46', 78, 78'). The device (40, 61-13, 61-15, 61-18, 61-19) comprises a substrate (48, 72) with upper (37) and lower (63, 73) surfaces. A semiconductor (38, 72) is located proximate the upper surface (37) with a device region (26) therein. One or more cavities (67, 77) underlying the device region (26) are etched in the substrate (48, 72) from the lower surface (63, 73). A higher thermal conductivity material (68) versus the substrate (48, 72) fills the one or more cavities (67) and has an exposed surface (69, 69', 79, 79') underlying the device region (26) at or beyond the lower surface (63, 73). This provides the under-filled heat extractor(s) (46, 46', 78, 78'). A composite substrate (48) is preferred, having a first semiconductor (38) extending to the upper surface (37) containing the device region (26), a second semiconductor (42) extending to the lower surface (63) and an insulating layer (36) therebetween, wherein the one or more cavities (67) extend from the lower surface (63) to the insulating layer (36) and the etch depth (671) is self limiting.
Abstract translation: 提供了一种半导体器件(40,61-13,61-19,61-15,61-18,61-19)和方法(60-5 ... 60-19,100,200) (46,46',78,78')。 装置(40,61-13,61-15,61-18,61-19)包括具有上(37)和下(63,73)表面的基底(48,72)。 半导体(38,72)位于靠近上表面(37)处,其中具有器件区域(26)。 下部表面(63,73)在衬底(48,72)中蚀刻位于器件区域(26)下面的一个或多个腔体(67,77)。 较高的导热材料(68)相对于基底(48,72)填充一个或多个空腔(67),并且在装置区域(26)下方的暴露表面(69,69',79,79')处于或 超出下表面(63,73)。 这提供了未填充的散热器(46,46',78,78')。 复合衬底(48)是优选的,具有延伸到包含器件区域(26)的上表面(37)的第一半导体(38),延伸到下表面(63)的第二半导体(42)和绝缘层 (36),其中所述一个或多个空腔(67)从所述下表面(63)延伸到所述绝缘层(36),并且所述蚀刻深度(671)是自限制的。
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公开(公告)号:WO2007041007A3
公开(公告)日:2008-01-24
申请号:PCT/US2006036831
申请日:2006-09-20
Applicant: FREESCALE SEMICONDUCTOR INC , CHUNG YOUNG SIR , BAIRD ROBERT W , DURLAM MARK A
Inventor: CHUNG YOUNG SIR , BAIRD ROBERT W , DURLAM MARK A
IPC: G11B5/33
CPC classification number: G11C11/16 , G01K7/01 , G11C29/50 , G11C29/50008 , G11C2029/5002
Abstract: An integrated circuit device (600) is provided which includes a heat source (604) disposed in a substrate (602), and a Magnetic Tunnel Junction ("MTJ") temperature sensor (608) disposed over the heat source.
Abstract translation: 提供了集成电路装置(600),其包括设置在基板(602)中的热源(604)和设置在热源上方的磁隧道结(“MTJ”)温度传感器(608)。
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公开(公告)号:WO2007041007A2
公开(公告)日:2007-04-12
申请号:PCT/US2006/036831
申请日:2006-09-20
Applicant: FREESCALE SEMICONDUCTOR INC. , CHUNG, Young Sir , BAIRD, Robert W. , DURLAM, Mark A.
Inventor: CHUNG, Young Sir , BAIRD, Robert W. , DURLAM, Mark A.
IPC: G11B5/33
CPC classification number: G11C11/16 , G01K7/01 , G11C29/50 , G11C29/50008 , G11C2029/5002
Abstract: An integrated circuit device (600) is provided which includes a heat source (604) disposed in a substrate (602), and a Magnetic Tunnel Junction ("MTJ") temperature sensor (608) disposed over the heat source.
Abstract translation: 提供了集成电路装置(600),其包括设置在基板(602)中的热源(604)和设置在热源上方的磁隧道结(“MTJ”)温度传感器(608)。
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公开(公告)号:WO2007016011A2
公开(公告)日:2007-02-08
申请号:PCT/US2006/028576
申请日:2006-07-24
Applicant: FREESCALE SEMICONDUCTOR , CHUNG, Young Sir , BAIRD, Robert, W. , ENGEL, Bradley, N.
Inventor: CHUNG, Young Sir , BAIRD, Robert, W. , ENGEL, Bradley, N.
CPC classification number: G01R33/06
Abstract: Methods and apparatus are provided for sensing physical parameters. The apparatus (130) comprises a magnetic tunnel junction (MTJ) [32] and a magnetic field source (34) whose magnetic field (35) overlaps the MTJ and whose proximity to the MTJ varies in response to an input to the sensor. The MTJ comprises first and second magnetic electrodes (36,38) separated by a dielectric (37) configured to permit significant tunneling conduction therebetween. The first magnetic electrode has its spin axis pinned and the second magnetic electrode has its spin axis free. The magnetic field source is oriented closer to the second magnetic electrode than the first magnetic electrode. The overall sensor dynamic range is extended by providing multiple electrically coupled sensors receiving the same input but with different individual response curves and desirably but not essentially formed on the same substrate.
Abstract translation: 提供了用于感测物理参数的方法和装置。 该装置(130)包括一个磁性隧道结(MTJ)[32]和一个磁场源(34),其磁场(35)与MTJ重叠,并且其与MTJ的接近度响应于传感器的输入而变化。 MTJ包括由电介质(37)分开的第一和第二磁极(36,38),其被配置为允许它们之间的显着的隧穿传导。 第一磁极的自旋轴被固定,第二磁极具有自由轴。 磁场源比第一磁极更靠近第二磁极。 通过提供多个电耦合传感器来接收相同的输入但是具有不同的单个响应曲线并且期望地但不是基本上形成在相同的基板上来扩展总传感器动态范围。
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公开(公告)号:WO2007005303A3
公开(公告)日:2007-01-11
申请号:PCT/US2006/024228
申请日:2006-06-22
Applicant: FREESCALE SEMICONDUCTOR , GRYNKEWICH, Gregory W. , CHUNG, Young Sir , BAIRD, Robert W. , DURLAM, Mark A. , SALTER, Eric J.
Inventor: GRYNKEWICH, Gregory W. , CHUNG, Young Sir , BAIRD, Robert W. , DURLAM, Mark A. , SALTER, Eric J.
IPC: G11C11/00
Abstract: An integrated circuit device (300) includes a magnetic random access memory ("MRAM") architecture and a smart power integrat circuit architecture formed on the same substrate (302) using the same fabrication process technology The fabrication process technology is a modular process having a front end process and a back end process In the example embodiment, the smart power architecture includes a power circuit component (304), a digital logic component (306), and an analog control component (312) form by the front end process, and a sensor architecture (308) formed by the back end process The MRAM architecture (310) includes an MRAM circuit component (314) formed by the front end process and an MRAM cell array (316) formed by the back end process In one practical embodiment, the sensor architecture (308) includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array (316).
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26.
公开(公告)号:WO2007040991A3
公开(公告)日:2009-04-16
申请号:PCT/US2006036634
申请日:2006-09-20
Applicant: FREESCALE SEMICONDUCTOR INC , CHUNG YOUNG SIR , BAIRD ROBERT W , DURLAM MARK A
Inventor: CHUNG YOUNG SIR , BAIRD ROBERT W , DURLAM MARK A
IPC: H01L21/00
CPC classification number: H01L27/228 , G01K7/36 , Y10T428/1114
Abstract: Techniques of sensing a temperature of a heat source disposed in a substrate of an integrated circuit (600) are provided. According to one exemplary method, a Magnetic Tunnel Junction ("MTJ") temperature sensor (608) is provided over the heat source (604). The MTJ temperature sensor comprises an MTJ core configured to output a current during operation thereof. The value of the current varies based on a resistance value of the particular MTJ core. The resistance value of the MTJ core varies as a function of the temperature of the heat source. A value of the current of the MTJ core can then be associated with a corresponding temperature of the heat source.
Abstract translation: 提供了感测设置在集成电路(600)的基板中的热源的温度的技术。 根据一个示例性方法,在热源(604)之上提供磁隧道结(“MTJ”)温度传感器(608)。 MTJ温度传感器包括被配置为在其操作期间输出电流的MTJ内核。 电流值根据特定MTJ磁芯的电阻值而变化。 MTJ芯的电阻值随着热源的温度而变化。 然后,MTJ芯的电流的值可以与热源的相应温度相关联。
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公开(公告)号:WO2007018811A2
公开(公告)日:2007-02-15
申请号:PCT/US2006/025259
申请日:2006-06-28
Applicant: FREESCALE SEMICONDUCTOR , CHUNG, Young Sir , BAIRD, Robert W.
Inventor: CHUNG, Young Sir , BAIRD, Robert W.
IPC: H01L21/00
CPC classification number: G01R33/093 , B82Y25/00 , B82Y40/00 , G01R33/098 , G11C11/16 , H01F41/307
Abstract: Methods and apparatus are provided for sensing physical parameters. The apparatus (30) comprises a magnetic tunnel junction (MTJ) (32) and a magnetic field source (34) whose magnetic field (35) overlaps the MTJ and whose proximity to the MTJ varies in response to an input to the sensor. The MTJ comprises first and second magnetic electrodes (36, 38) separated by a dielectric (37) configured to permit significant tunneling conduction therebetween. The first magnetic electrode has its spin axis pinned and the second magnetic electrode has its spin axis free. The magnetic field source is oriented closer to the second magnetic electrode than the first magnetic electrode. The overall sensor dynamic range is extended by providing multiple electrically coupled sensors receiving the same input but with different individual response curves and desirably but not essentially formed on the same substrate.
Abstract translation: 提供了用于感测物理参数的方法和设备。 装置(30)包括磁性隧道结(MTJ)(32)和磁场源(34),磁性源的磁场(35)与MTJ重叠,并且其与MTJ的接近度响应于到传感器的输入而变化。 MTJ包括由电介质(37)分开的第一和第二磁电极(36,38),电介质(37)配置为允许其间的显着的隧道传导。 第一磁性电极的自旋轴固定,第二磁性电极的自旋轴自由。 磁场源比第一磁性电极更靠近第二磁性电极。 整个传感器动态范围通过提供多个电耦合传感器来扩展,所述多个电耦合传感器接收相同的输入但具有不同的单独响应曲线并且理想地但不基本形成在相同衬底上。 p>
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28.
公开(公告)号:WO2007016009A2
公开(公告)日:2007-02-08
申请号:PCT/US2006/028573
申请日:2006-07-24
Applicant: FREESCALE SEMICONDUCTOR , CHUNG, Young Sir , BAIRD, Robert, W. , GRYNKEWICH, Gregory, W.
Inventor: CHUNG, Young Sir , BAIRD, Robert, W. , GRYNKEWICH, Gregory, W.
IPC: G11B5/127
CPC classification number: G01R33/06 , H01L43/12 , Y10T29/49032 , Y10T29/49034 , Y10T29/49036 , Y10T29/49039 , Y10T29/49041 , Y10T29/49043 , Y10T29/49044
Abstract: Methods and apparatus are provided for sensing physical parameters. The apparatus (30) comprises a magnetic tunnel junction (MTJ) [32] and a magnetic field source (34) whose magnetic field (35) overlaps the MTJ and whose proximity to the MTJ varies in response to an input to the sensor. A magnetic shield (33) is provided at least on a face of the MFS away from the MTJ. The MTJ comprises first and second magnetic electrodes (36, 38) separated by a dielectric (37) configured to permit significant tunneling conduction therebetween. The first magnetic region has its spin axis pinned and the second magnetic electrode has its spin axis free. The magnetic field source is oriented closer to the second magnetic electrode than the first magnetic electrode. The overall sensor dynamic range is extended by providing multiple electrically coupled sensors receiving the same input but with different individual response curves and desirably but not essentially formed on the same substrate.
Abstract translation: 提供了用于感测物理参数的方法和装置。 该装置(30)包括一个磁性隧道结(MTJ)[32]和一个磁场源(34),其磁场(35)与MTJ重叠,并且其与MTJ的接近度响应于传感器的输入而变化。 至少在远离MTJ的MFS的面上设有磁屏蔽(33)。 MTJ包括由电介质(37)分开的第一和第二磁极(36,38),其被配置为允许它们之间的显着的隧道传导。 第一磁性区域的自旋轴被固定,第二磁极的自由轴自由。 磁场源比第一磁极更靠近第二磁极。 通过提供多个电耦合传感器来接收相同的输入但是具有不同的单个响应曲线并且期望地但不是基本上形成在相同的基板上来扩展总传感器动态范围。
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公开(公告)号:WO2007005303A2
公开(公告)日:2007-01-11
申请号:PCT/US2006024228
申请日:2006-06-22
Applicant: FREESCALE SEMICONDUCTOR INC , GRYNKEWICH GREGORY W , CHUNG YOUNG SIR , BAIRD ROBERT W , DURLAM MARK A , SALTER ERIC J
Inventor: GRYNKEWICH GREGORY W , CHUNG YOUNG SIR , BAIRD ROBERT W , DURLAM MARK A , SALTER ERIC J
IPC: G11C11/14
CPC classification number: G11C11/1659 , H01F10/3254
Abstract: An integrated circuit device (300) includes a magnetic random access memory ("MRAM") architecture and a smart power integrated circuit architecture formed on the same substrate (302) using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component (304), a digital logic component (306), and an analog control component (312) formed by the front end process, and a sensor architecture (308) formed by the back end process. The MRAM architecture (310) includes an MRAM circuit component (314) formed by the front end process and an MRAM cell array (310) formed by the back end process. In one practical embodiment, the sensor architecture (308) includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array (316). The concurrent fabrication of the MRAM architecture (310) and the smart power architecture facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.
Abstract translation: 集成电路器件(300)包括磁性随机存取存储器(“MRAM”)结构和使用相同制造工艺技术在相同衬底(302)上形成的智能功率集成电路架构。 制造工艺技术是具有前端工艺和后端工艺的模块化工艺。 在该示例实施例中,智能电力架构包括由前端处理形成的电源电路部件(304),数字逻辑部件(306)和模拟控制部件(312),以及传感器架构(308),由 后端进程。 MRAM架构(310)包括由前端处理形成的MRAM电路部件(314)和由后端处理形成的MRAM单元阵列(310)。 在一个实际的实施例中,传感器架构(308)包括由MRAM单元阵列(316)使用的相同的磁性隧道结芯体材料形成的传感器部件。 MRAM架构(310)和智能电源架构的并行制造有助于在衬底的有源电路块上可用的物理空间的有效且成本有效的使用,导致三维集成。
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公开(公告)号:WO2006007142A3
公开(公告)日:2006-03-16
申请号:PCT/US2005017703
申请日:2005-05-19
Applicant: FREESCALE SEMICONDUCTOR INC , MANCINI DAVID P , CHUNG YOUNG , DAUKSHER WILLIAM J , WESTON DONALD F , YOUNG STEVEN R , BAIRD ROBERT W
Inventor: MANCINI DAVID P , CHUNG YOUNG , DAUKSHER WILLIAM J , WESTON DONALD F , YOUNG STEVEN R , BAIRD ROBERT W
IPC: H01L21/301 , H01L21/46
CPC classification number: H01L21/3065 , H01L21/78 , Y10S438/977
Abstract: In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions (42, 43) are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.
Abstract translation: 根据具体实施例,公开了一种处理半导体衬底的方法,由此使衬底变薄,并且通过公共工艺将形成在衬底上的裸片分割。 沟槽区域(42,43)形成在衬底的背面。 背面的各向同性蚀刻导致衬底的薄化,同时保持沟槽的深度,从而有利于模具的分离。
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