公开(公告)号：WO2020152563A1

公开(公告)日：2020-07-30

申请号：PCT/IB2020/050407

申请日：2020-01-20

Applicant: FONDAZIONE ISTITUTO ITALIANO DI TECNOLOGIA ,  AB ANALITICA S.R.L. ,  INSTITUTE DE BIOLOGIE INTEGRATIVE DE LA CELLULE (12BC), CNRS/UNIVERSITÉ PARIS SUD/CEA ,  ALACRIS THERANOSTICS GMBH

Inventor： DE ANGELIS, Francesco ,  GAROLI, Denis ,  ROCCHIA, Walter ,  SPITALERI, Andrea ,  HILDEBRANDT, Niko ,  PALADIN, Dino ,  SCHUETTE, Moritz ,  LEHRACH, Hans Rudolf

IPC: G01N33/542 ,  G01N33/68 ,  C12Q1/6869 ,  B82B1/00 ,  B82Y15/00

Abstract: The present invention relates to a method, an apparatus and a nanopore for optical recognition of molecules, wherein said method comprises a step wherein a molecule (4) to be recognized passes through a nanopore (1), and is characterized in that the nanopore (1) comprises at least one flexible element (10) configured substantially as an appendix or the like, extending within the nanopore (1), and wherein the recognition step is effected in relation to the displacement and/or deformation of the flexible element (10) induced by the passage of the molecule (4).

公开(公告)号：WO2018065741A2

公开(公告)日：2018-04-12

申请号：PCT/FR2017/052748

申请日：2017-10-06

Applicant: COMMISSARIAT À L’ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES (CEA)

Inventor： MALLOGGI, Florent ,  MESBAH, Kiarach ,  BREGANT, Sarah

Abstract: La présente invention concerne un procédé de concentration d'au moins un analyte (11) comprenant les étapes suivantes : préparation d'une première phase (1) comprenant au moins un analyte (11); dépôt d'une goutte de ladite première phase (1) sur un substrat (2); dépôt sur ladite goutte de première phase (1) d'une goutte d'une seconde phase (4) liquide comprenant au moins un tensioactif (41), ladite seconde phase (4) étant non miscible avec ladite première phase (1); évaporation de la goutte de la seconde phase (4); et évaporation de la goutte de la première phase (1). La présente invention concerne également un procédé de détection d'au moins un analyte (11) mettant en œuvre ledit procédé de concentration; et un système mettant en œuvre ledit procédé de détection.

Abstract translation: 解码方法技术领域本发明涉及一种解码方法 包含以下步骤的至少一种分析物（11）的浓度：制备包含至少一种分析物（11）的第一相（1）; 在基底（2）上沉积一滴所述第一相（1）; 在包含至少一种表面活性剂（41）的第二液相（4）的所述第一相（1）滴下，所述第二相（4）不与 所述第一阶段（1）; 第二阶段（4）下降的蒸发; 和第一阶段（1）的下降的蒸发。 本发明还涉及一种净化方法。 检测包含所述解除接触方法的至少一种分析物（11） 浓度; 以及实施所述方法的系统; 的检测。

公开(公告)号：WO2017095409A1

公开(公告)日：2017-06-08

申请号：PCT/US2015/063613

申请日：2015-12-03

Applicant: INTEL CORPORATION ,  MEHANDRU, Rishabh ,  KOTLYAR, Roza ,  CEA, Stephen, M. ,  KEYS, Patrick, H.

Inventor： MEHANDRU, Rishabh ,  KOTLYAR, Roza ,  CEA, Stephen, M. ,  KEYS, Patrick, H.

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L21/8221 ,  H01L21/823807 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/1054

Abstract: Disclosed herein are stacked channel structures for metal oxide semiconductor field effect transistors (MOSFETs) and related circuit elements, computing devices, and methods. For example, a stacked channel structure may include: a semiconductor substrate having a substrate lattice constant; a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region; a first transistor in the lower region, wherein the first transistor has a first channel, the first channel has a first lattice constant, and the first lattice constant is different from the substrate lattice constant; and a second transistor in the upper region, wherein the second transistor has a second channel, the second channel has a second lattice constant, and the second lattice constant is different from the substrate lattice constant.

Abstract translation: 这里公开了用于金属氧化物半导体场效应晶体管（MOSFET）和相关电路元件，计算设备和方法的堆叠沟道结构。 例如，堆叠沟道结构可以包括：具有衬底晶格常数的半导体衬底; 延伸离开所述半导体衬底的鳍片，所述鳍片具有上部区域和下部区域; 在所述下部区域中的第一晶体管，其中所述第一晶体管具有第一沟道，所述第一沟道具有第一晶格常数，并且所述第一晶格常数不同于所述衬底晶格常数; 以及在上部区域中的第二晶体管，其中第二晶体管具有第二沟道，第二沟道具有第二晶格常数，并且第二晶格常数不同于衬底晶格常数。

公开(公告)号：WO2014099013A1

公开(公告)日：2014-06-26

申请号：PCT/US2013/047988

申请日：2013-06-26

Applicant: INTEL CORPORATION ,  GLASS, Glenn, A. ,  AUBERTINE, Daniel, B. ,  MURTHY, Anand, S. ,  THAREJA, Gaurav ,  CEA, Stephen M.

Inventor： GLASS, Glenn, A. ,  AUBERTINE, Daniel, B. ,  MURTHY, Anand, S. ,  THAREJA, Gaurav ,  CEA, Stephen M.

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/16 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0669 ,  H01L29/1033 ,  H01L29/785 ,  H01L29/7853

Abstract: Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例提供了与从硅（Si）到硅锗（SiGe）的薄晶体管元件的转换相关联的技术和配置。 在一个实施例中，一种方法包括提供具有设置在半导体衬底上的晶体管器件的沟道体的半导体衬底，沟道体包括硅，在沟道本体上形成包含锗的包覆层，并使通道体退火， 锗扩散到通道体内。 可以描述和/或要求保护其他实施例。

公开(公告)号：WO2014018181A1

公开(公告)日：2014-01-30

申请号：PCT/US2013/045440

申请日：2013-06-12

Applicant: INTEL CORPORATION ,  CEA, Stephen M. ,  MURTHY, Anand S. ,  GLASS, Glenn A. ,  AUBERTINE, Daniel B. ,  GHANI, Tahir ,  KAVALIEROS, Jack T. ,  KOTLYAR, Roza

Inventor： CEA, Stephen M. ,  MURTHY, Anand S. ,  GLASS, Glenn A. ,  AUBERTINE, Daniel B. ,  GHANI, Tahir ,  KAVALIEROS, Jack T. ,  KOTLYAR, Roza

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/1054 ,  H01L21/76224 ,  H01L29/06 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric / semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric / semiconductor interface.

Abstract translation: 公开了用于将高迁移率应变通道结合到鳍状晶体管（例如，诸如双栅极，三相等等的FinFET）中的技术，其中应力材料被包覆到鳍的沟道区域上。 在一个示例性实施例中，硅锗（SiGe）被包覆到硅散热片上以提供期望的应力，尽管可以使用其它鳍和包层材料。 这些技术与典型的工艺流程兼容，并且包层沉积可以发生在工艺流程内的多个位置处。 在一些情况下，来自包覆层的内置应力可以通过压缩通道中的鳍和覆层的源极/漏极应力来增强。 在一些情况下，可以提供可选的封盖层以改善栅极电介质/半导体界面。 在一个这样的实施例中，硅被提供在SiGe包覆层上以改善栅极电介质/半导体界面。

公开(公告)号：WO2013187817A1

公开(公告)日：2013-12-19

申请号：PCT/SE2012/050822

申请日：2012-07-10

Applicant: Telefonaktiebolaget L M Ericsson (publ) ,  LAU, Katrina ,  GOODWIN, Graham C ,  CEA, Mauricio ,  BRUS, Linda

Inventor： LAU, Katrina ,  GOODWIN, Graham C ,  CEA, Mauricio ,  BRUS, Linda

IPC: H04L1/00 ,  H04W28/02 ,  H04W72/12 ,  H04L12/835

CPC classification number: H04W72/1278 ,  H04L1/0002 ,  H04L1/0018 ,  H04L1/0035 ,  H04L47/30 ,  H04W28/02 ,  H04W72/12

Abstract: A method may be provided to operate a node of a radio access network communicating with a wireless terminal. The wireless terminal may be configured to provide a transmit buffer for data to be transmitted to the node during transmission time intervals, to transmit packets of the data from the transmit buffer to the node during respective transmission time intervals, and to provide buffer indicator bits with respective packets of the data during the respective transmission time intervals. The method may include: receiving a packet including data and a buffer indicator bit from the wireless terminal during a respective transmission time interval; and providing an estimate of a quantity of data in the transmit buffer at the wireless terminal responsive to a status of the buffer indicator bit. Related wireless terminals and network nodes are also discussed.

Abstract translation: 可以提供一种方法来操作与无线终端通信的无线电接入网络的节点。 无线终端可以被配置为在传输时间间隔期间为要发送到节点的数据提供发送缓冲器，以在各个传输时间间隔期间将数据从发送缓冲器发送到节点，并且提供缓冲区指示符位与 在相应的传输时间间隔期间数据的各个分组。 该方法可以包括：在相应的传输时间间隔期间从无线终端接收包括数据和缓冲区指示符比特的分组; 以及响应于所述缓冲器指示符位的状态，在所述无线终端处提供所述发送缓冲器中的数据量的估计。 还讨论了相关的无线终端和网络节点。

公开(公告)号：WO2013095652A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/067236

申请日：2011-12-23

Applicant: INTEL CORPORATION ,  CEA, Stephen M. ,  KIM, Seiyon ,  CAPPELLANI, Annalisa

Inventor： CEA, Stephen M. ,  KIM, Seiyon ,  CAPPELLANI, Annalisa

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/1054 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

Abstract: Uniaxially strained nanowire structures are described. For example, a semiconductor device includes a plurality of vertically stacked uniaxially strained nanowires disposed above a substrate. Each of the uniaxially strained nanowires includes a discrete channel region disposed in the uniaxially strained nanowire. The discrete channel region has a current flow direction along the direction of the uniaxial strain. Source and drain regions are disposed in the nanowire, on either side of the discrete channel region. A gate electrode stack completely surrounds the discrete channel regions.

Abstract translation: 描述了单轴应变纳米线结构。 例如，半导体器件包括设置在衬底上方的多个垂直堆叠的单轴应变纳米线。 单轴应变纳米线中的每一个包括设置在单轴应变纳米线中的离散通道区域。 离散通道区域沿着单轴应变的方向具有电流流动方向。 源极和漏极区域设置在离散通道区域的任一侧上的纳米线中。 栅极电极堆叠完全围绕离散通道区域。

公开(公告)号：WO2013095647A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/067226

申请日：2011-12-23

Applicant: INTEL CORPORATION ,  CEA, Stephen M. ,  WEBER, Cory E. ,  KEYS, Patrick H. ,  KIM, Seiyon ,  HAVERTY, Michael G. ,  SHANKAR, Sadasivan

Inventor： CEA, Stephen M. ,  WEBER, Cory E. ,  KEYS, Patrick H. ,  KIM, Seiyon ,  HAVERTY, Michael G. ,  SHANKAR, Sadasivan

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78696

Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.

Abstract translation: 描述具有环绕触点的纳米线结构。 例如，纳米线半导体器件包括设置在衬底之上的纳米线。 沟道区域设置在纳米线中。 通道区域具有与长度正交的长度和周长。 栅电极堆叠围绕通道区域的整个周边。 一对源极和漏极区域设置在沟道区域的任一侧上的纳米线中。 源极和漏极区域中的每一个具有与沟道区域的长度正交的周长。 第一接触件完全围绕源区域的周边。 第二触点完全围绕漏区的周边。

公开(公告)号：WO2013029748A1

公开(公告)日：2013-03-07

申请号：PCT/EP2012/003429

申请日：2012-08-10

Applicant: CERN - EUROPEAN ORGANIZATION FOR NUCLEAR RESEARCH ,  CEA ,  DE OLIVEIRA, Rui ,  GIOMATARIS, loannis

Inventor： DE OLIVEIRA, Rui ,  GIOMATARIS, loannis

IPC: G01T1/29 ,  H01J47/02

CPC classification number: G01T1/185 ,  G01T1/2935 ,  H01J47/02

Abstract: A detector-readout interface for an avalanche particle detector comprises a resistive layer formed at a bottom side of a gas chamber and a dielectric layer formed under said resistive layer and is adapted for capacitive coupling to an external readout board. This provides a modular detector configuration in which the readout card and detector core can be combined freely and interchangeably. The readout board can even be removed or replaced without switching off the detector. At the same time, the configuration provides an effective protection against sparks and discharges, and in particular obliviates the need for additional protecting circuits. The configuration may be employed in any avalanche particle detector, such as the MicroMegas or GEM detectors.

Abstract translation: 用于雪崩粒子检测器的检测器 - 读出器接口包括形成在气体室的底侧的电阻层和形成在所述电阻层下面的电介质层，并适于电容耦合到外部读出板。 这提供了一种模块化检测器配置，其中读出卡和检测器芯可以自由地和可互换地组合。 读取板甚至可以拆下或更换，而不关闭检测器。 同时，该配置提供了有效的防止火花和放电的保护，特别是不再需要额外的保护电路。 该配置可以用于任何雪崩粒子检测器，例如MicroMegas或GEM检测器。

公开(公告)号：WO2012074872A2

公开(公告)日：2012-06-07

申请号：PCT/US2011/062059

申请日：2011-11-23

Applicant: INTEL CORPORATION ,  KUHN, Kelin J. ,  KIM, Seiyon ,  RIOS, Rafael ,  CEA, Stephen M. ,  GILES, Martin D. ,  CAPPELLANI, Annalisa ,  RAKSHIT, Titash ,  CHANG, Peter ,  RACHMADY, Willy

Inventor： KUHN, Kelin J. ,  KIM, Seiyon ,  RIOS, Rafael ,  CEA, Stephen M. ,  GILES, Martin D. ,  CAPPELLANI, Annalisa ,  RAKSHIT, Titash ,  CHANG, Peter ,  RACHMADY, Willy

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Abstract translation: 描述了形成微电子结构的方法。 那些方法的实施例包括形成包括衬底的纳米线器件，所述衬底包括与间隔物相邻的源极/漏极结构以及设置在间隔物之间​​的纳米线沟道结构，其中纳米线沟道结构垂直堆叠在彼此之上。