Abstract:
Customisable embedded processors that are available on the market make it possible for designers to speed up execution of applications by using Application-specific Functional Units (AFUs), implementing Instruction-Set Extensions (ISEs). Furthermore, techniques for automatic ISE identification have been improving; many algorithms have been proposed for choosing, given the application's source code, the best ISEs under various constraints. Read and write ports between the AFUs and the processor register file are an expensive asset, fixed in the micro-architecture - some processors indeed only allow two read ports and one write port - and yet, on the other hand, a large availability of inputs and outputs to and from the AFUs exposes high speedup. Here we present a solution to the limitation of actual register file ports by serialising register file access and therefore addressing multi-cycle read and write. It does so in an innovative way for two reasons: (1) it exploits and brings forward the progress in ISE identification under constraint, and (2) it combines register file access serialisation with pipelining in order to obtain the best global solution. Our method consists of scheduling graphs - corresponding to ISEs - under input/ output constraint
Abstract:
The aim of the present invention is to propose a method to provide reliability, power management and load balancing support for multicore systems based on Networks- on-Chip (NoCs) as well as a way to efficiently implement architectural support for this method by introducing complex packet handling mechanisms achieved by modifying the basic network interfaces attached to the cores of multicore computation systems. The present invention provides also a solution in interrupt-based support in NoCs for multicore computation systems against transient failures or other system-level issues while the system is executing a certain application. It also proposes policies to leverage the proposed hardware extensions. This aim is achieved thanks to a method to manage the load of peripheral elements within a multicore system, said multicore system comprising several processing cores accessing peripheral elements through a Network on Chip (NoC), each processing unit and peripheral element attached to a Network Interface in charge of formatting and driving the packets sent to or received from the Network on Chip, wherein, while considering at least two peripheral elements having a similar function, the Network Interface dedicated to a first peripheral element reroutes the incoming packets to a second Network Interface dedicated to a second peripheral element.
Abstract:
The invention relates to video and/or image data processing with determination of representation functions. According to the invention, one device (DT) is dedicated to processing n-dimensional input data that are representative of an image or a sequence of images with n dimensions corresponding to n directions, whereby n = 2. The invention comprises processing means (MT) which, upon receipt of input data, perform the following steps consisting in: (i) defining one or more connecting n-dimensional domains having complementary shapes which are defined by position data and containing input data; (ii) subsequently, for each n-dimensional domain, determining a representation function that is representative of the set of input data contained therein and constructed from basic functions selected from at least one database of basic functions and respectively associated with selected coefficients, whereby said representation functions can be connected in pairs at least; and (iii) transforming at least some of the coefficients of at least one of the representation functions into representation data which, together with the associated position data, define output data that are representative of the input data.
Abstract:
The invention concerns a method for making a matrix flat display active plate, wherein each cell comprises an electrode plate (1), connected by a transistor (2) to a first conductive line, including the following steps: providing a protuberance (11) coated with insulation of each first conductive line at each cell; etching or making porous an end part of each protuberance; growing by VLS process a p-i-p or n-i-n semiconductor structure in each etched or porous end part; and establishing a contact at the free end of the semiconductor structure and forming a gate at the median part of the semiconductor structure.
Abstract:
A Hall sensor comprises a Hall element (1; 30; 31; 60) and an amplifier (2; 32; 33). The Hall element is placed inside the amplifier so that the current flowing through the Hall element also flows through the transistors of an amplifier stage of the amplifier. The current flowing through the Hall element flows for example through the transistors of an input stage of the amplifier. In doing so the current consumption of the Hall sensor is reduced to the current the amplifier consumes itself. The Hall sensor is preferably operated in a modified spinning current method that preserves the correlation of the noise as far as possible. Preferably, the current flowing through the Hall element is pulsed. This mode of operation is useful for applications based on a battery as power supply. The signal to noise ratio related to the power consumption increases. A pulsed operation means that the current flowing through the Hall element is switched on and off with a predetermined frequency.
Abstract:
A method for including an oxide region in a layered structure being grown epitaxially on a substrate, comprising the steps of epitaxially forming a Group III-nitride precursor layer, and selectively oxidizing the precursor layer, thereby forming the oxide region.
Abstract:
The invention relates to a device for measuring the quality and/or degradation of a fluid, especially an oil, comprising a sensor consisting of at least one pair of electrodes which are distanced from each other. Said sensor is immersed in the fluid which is to be measured. The electrodes and the fluid form a capacitive element whose capacity varies according to the dielectric constant of the fluid. The sensor can provide an electric output signal representing said dielectric constant. The inventive device also comprises processing means which receive the output signal and which can determine the degree of quality and/or degradation of the fluid on the basis of said output signal. The invention is characterized in that the electrodes extend substantially on the same plane and in that the fluid surrounds the two surfaces of the electrodes on both sides of said plane.
Abstract:
The present invention relates to a method of producing a high density pattern of isolated clusters on a surface of a substrate, comprising treating the surface of the substrate to produce element-adhesion sites distributed on the surface of the substrate in accordance with the pattern, depositing a first transition series element on the surface of the substrate, and forming, by diffusion and/or coalescence, clusters of the deposited element on the elementadhesion sites. The size of the clusters can be manipulated by irradiating the clusters with a low energy ion beam to cause coalescence of the clusters and diffusion of these clusters on the surface of the substrate whereby the size of the clusters is changed. The surface of the substrate can also be irradiated at a grazing angle with a low energy ion beam to modify the surface of the substrate and thereby enhance adhesion of the clusters of the deposited element to the modified surface. Finally, contact mode atomic force microscopy can be used for surface local cleaning and cluster assembling by applying an atomic force microscopy tip to the surface of the substrate and scanning with this tip a region of the substrate surface.
Abstract:
An electrically pumped VCSEL (10) and a method of its fabrication are presented. The VCSEL (10) comprises an active cavity material (14) sandwiched between top and bottom DBR stacks (12a, 12b), the top DBR (12b) having at least one n-semiconductor layer. The device defines an aperture region (25) between the structured surface (14b) of the active cavity material (14) and the n-semiconductor layer of the top DBR stack (12b). The structured surface (14b) is formed by a top surface of a mesa (22) that includes at least the upper n layer of a p /n tunnel junction and the surface of a p-type layer outside the mesa (22). The structured surface (14b) is fused to the surface of the n-semiconductor layer of the DBR stack (12b) due to the deformation of these surfaces, thereby creating an air gap (24) in the vicinity of the mesa (22) between the fused surfaces. The active region is defined by the current aperture (25) which includes the mesa (22) surrounded by the air gap (24), thereby allowing for restricting an electrical current flow to the active region, while the air gap (24) provides for the lateral variation of the index of refraction in the VCSEL (10).