公开(公告)号：WO1996037983A1

公开(公告)日：1996-11-28

申请号：PCT/US1996007105

申请日：1996-05-16

Applicant: HYUNDAI ELECTRONICS AMERICA, INC. ,  RAO, R., Padmanabha ,  SICCARDO, Paolo, L. ,  LEVESQUE, Gilbert

Inventor： HYUNDAI ELECTRONICS AMERICA, INC.

IPC: H04L05/16

CPC classification number: H04N7/17336 ,  H04H20/38 ,  H04H20/81 ,  H04H60/94 ,  H04L12/2801 ,  H04L12/2856 ,  H04L12/2883 ,  H04L12/4633 ,  H04L47/2408 ,  H04M11/062 ,  H04N7/108 ,  H04N7/148 ,  H04N7/173 ,  H04N7/17354 ,  H04N21/222 ,  H04N21/2362 ,  H04N21/2365 ,  H04N21/4347 ,  H04N21/47202 ,  H04N21/47208 ,  H04N21/6125 ,  H04N21/6137 ,  H04N21/6377 ,  H04N21/64307 ,  H04N21/64784 ,  H04N21/658 ,  H04N21/6581 ,  H04N21/6587

Abstract: An architecture (200) for distributing digital information to subscriber units (202) wherein selection from among multiple digital services is accomplished by transmitting a tuning command from a subscriber unit to an intermediate interface (206). The intermediate interface (206) selects the desired service from a broadband network and transmits it to the subscriber unit (202) over a bandwidth-constrained access line. The bandwidth-constrained access line may be implemented with existing infrastructure, yet the subscriber unit (202) may access a wide variety of digital information available on the broadband network. Universal broadband access is thus provided at low cost. Output bandwidth of broadcast equipment may also be optimized.

Abstract translation: 一种用于向用户单元（202）分发数字信息的架构（200），其中通过从用户单元向中间接口（206）发送调谐命令来实现多个数字服务之间的选择。 中间接口（206）从宽带网络中选择所需的服务，并通过带宽限制的接入线路将其发送到用户单元（202）。 带宽有限的接入线路可以用现有的基础设施来实现，而用户单元（202）可以访问宽带网络上可用的各种数字信息。 因此以低成本提供通用宽带接入。 广播设备的输出带宽也可以优化。

公开(公告)号：WO1996034335A1

公开(公告)日：1996-10-31

申请号：PCT/US1996004504

申请日：1996-04-02

Applicant: HYUNDAI ELECTRONICS AMERICA, INC. ,  METAFLOW TECHNOLOGIES, INC.

Inventor： HYUNDAI ELECTRONICS AMERICA, INC. ,  METAFLOW TECHNOLOGIES, INC. ,  ISAMAN, David, L.

IPC: G06F09/30

CPC classification number: G06F9/30094 ,  G06F9/30101 ,  G06F9/327 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3861

Abstract: Apparatus for detecting and executing trapping program instructions in a superscalar processor operating on a plurality of pipelined instructions includes a fetch stage for fetching consecutive instructions from an instruction cache (210) or from main memory, an instruction FIFO memory (220) for storing fetched instructions from the fetch stage, and an instruction decode stage (230) for removing instructions from the FIFO memory (220) in accordance with relative ages of instructions stored in the FIFO memory (220). The decode stage examines instructions removed from the FIFO memory (220) for trapping conditions, and flushes all younger instructions from the FIFO memory (220) in response to identification of a trap in an instruction. The decode stage (230) distinguishes between hardware traps and software traps. A software trapping instruction is forwarded to an execute stage for execution. The decode stage (230) immediately causes the fetch address to be changed to the appropriate trap handler address.

Abstract translation: 用于检测和执行在多个流水线指令上操作的超标量处理器中的捕获程序指令的装置包括：用于从指令高速缓存（210）或从主存储器取出连续指令的提取级，用于存储读取的指令的指令FIFO存储器（220） 以及用于根据存储在FIFO存储器（220）中的指令的相对年龄从FIFO存储器（220）去除指令的指令解码级（230）。 解码阶段检查从FIFO存储器（220）中移除的用于捕获条件的指令，并且响应于指令中的陷阱的识别，刷新来自FIFO存储器（220）的所有较年轻的指令。 解码级（230）区分硬件陷阱和软件陷阱。 软件陷阱指令被转发到执行阶段执行。 解码级（230）立即使获取地址更改为适当的陷阱处理程序地址。

公开(公告)号：WO1996021278A1

公开(公告)日：1996-07-11

申请号：PCT/US1995017051

申请日：1995-12-29

Applicant: HYUNDAI ELECTRONICS AMERICA, INC.

Inventor： HYUNDAI ELECTRONICS AMERICA, INC. ,  OH, Jong-Hoon

IPC: H03K21/00

CPC classification number: G11C7/1018 ,  H03K23/004

Abstract: A counter system has a first counter (1) seeded by several input signals and a second counter (2) seeded by at least a first output from the first counter. A selection signal is input to the second counter to select the use of either an interleaved count sequence or a sequential count sequence.

Abstract translation: 计数器系统具有由几个输入信号接合的第一计数器（1）和由第一计数器的至少第一输出种子的第二计数器（2）。 选择信号被输入到第二计数器以选择使用交错计数序列或顺序计数序列。

公开(公告)号：JPH10308902A

公开(公告)日：1998-11-17

申请号：JP19008596

申请日：1996-07-01

Applicant: HYUNDAI ELECTRONICS IND ,  HYUNDAI ELECTRONICS AMERICA

Inventor： PRATER JAMES S

IPC: G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  H01L27/14 ,  H04N1/00 ,  H04N1/195 ,  H04N5/335 ,  H04N17/00

Abstract: PROBLEM TO BE SOLVED: To test the pixel sensor circuit in an image array independently of the strength of image illuminance. SOLUTION: A drive voltage as to a reset FET 32 is provided selectively through a common output line. When no row access enable signal is applied to an array, a control enable test voltage is fed to a common line. A column line source follower circuit is controlled by a row access FET 40. Thus, another test voltage is fed to the common line through a reset switch and connected to a photodiode 38 via the reset FET 32. A variable reset voltage fed to a row line ROW is changed between a normal bias electrode VDD as to a pixel sensor and ground by using Pchannel and N-channel FETs connected in parallel.

公开(公告)号：JPH10285187A

公开(公告)日：1998-10-23

申请号：JP35966997

申请日：1997-12-26

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： WILLS JEFFREY MERLIN

IPC: H04Q3/00 ,  H04L12/56 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To provide an ATM switch which has distributed buffering for higher performance and makes a larger design module. SOLUTION: An ATM switch has plural input and output ports 23 and 24 which are separately connected to input and output channels, a switch block 25 that is connected between them and a back pressure signal circuit. The input ports have input buffers 21 which hold a cell that arrives from the input channel earlier than the input port can transmit it, and the output ports have output buffers 22 which hold a cell when the cell arrives from the switch block earlier than the output ports can communicate it. The back pressure signal circuit sends a signal from a congested output buffer, makes the buffers of the input ports stop transmission and stores a cell that is estimated by the output buffers in the input port buffers.

公开(公告)号：JPH10285186A

公开(公告)日：1998-10-23

申请号：JP35966897

申请日：1997-12-26

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： WILLS JEFFREY MERLIN

IPC: H04Q3/00 ,  H04L12/56 ,  H04Q11/04 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To provide an ATM switch which quickly distributes buffering action, maximizes fast transmission of time critical data and minimizes transmission loss in a back pressure system. SOLUTION: An input port 23 transmits a cell from an input buffer in response to plural priority levels. Each output port 23 has an output buffer that retains a cell when the cell arrives from the input port faster than that the output port transmits it. The output port also transmits a cell from the output buffer in response to plural priority levels. A back pressure signal circuit sends a signal from the congested output buffer to the input buffer that just transmits a cell to the output buffer through a switch structure 10, and stops the transmission of the input port buffer. An ATM switch drops a cell based on previously connected reference more than a cell priority level. A penalty is imposed on a sender who makes congestion cause data more, than other users of the ATM switch.

公开(公告)号：JPH10105460A

公开(公告)日：1998-04-24

申请号：JP22234497

申请日：1997-08-19

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： JENNINGS EARLE W

IPC: G06F12/14 ,  G06F12/08 ,  G06F21/24 ,  G06T1/20 ,  H04N5/907 ,  H04N7/26 ,  H04N7/50 ,  G06T1/00

Abstract: PROBLEM TO BE SOLVED: To provide a computer system which provides additional performance as against a demand application only by adding a small hardware. SOLUTION: A slave device for a host computer system, for example, consists of the combination of an embedded programmable controler, a non-volatite memory, a local RAM and interface logic. The host computer system treats the slave device by assuming that it is a hierarchical memory system like a regular disk drive which stores and retrieves a file. Moreover, the host computer system can program the controller so as to operate stored information including an image processing and/or data compression. The non-volatile memory includes the disk drive, a writing possible CD-ROM, an optical disk or a non-volatile solid state memory.

公开(公告)号：JPH1084054A

公开(公告)日：1998-03-31

申请号：JP14203197

申请日：1997-05-30

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： HSINGYA ARTHUR WANG ,  YOUNG JEIN-CHEN ,  MING-SANG KWAN ,  IIYUN CHOI

IPC: H01L21/8238 ,  H01L21/8247 ,  H01L27/092 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a flash memory operating at a lower potential. SOLUTION: The flash memory cell is appropriately manufactured in a silicon substrate 20. An N conductivity type silicon well 22 is formed in the P conductive type silicon made substrate 20. A P conductivity type well 24 is formed in the N well 22. For the ohmic contact with the P well 24, a region 28 additionally doped with a source 27 and a drain 26 is formed in the P well 24. Besides, a floating gate 29 and a control gate 21 are provided. Furthermore, a contact 25 to the N well 22 is provided for making feasible of the bias of the same.

公开(公告)号：JPH1055664A

公开(公告)日：1998-02-24

申请号：JP11945097

申请日：1997-05-09

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： PINKHAM RAY ,  YEO CHEOW F

IPC: G11C11/401 ,  G11C7/10 ,  G11C11/409

Abstract: PROBLEM TO BE SOLVED: To save the power consumption during the block write operation by freezing a normal writing data path during the block write cycle. SOLUTION: The video memory device is provided with a normal write mode and a block write mode, and also a large area writing driver for driving a large area input/output(I/O) line and many local writing drivers 120 are provided therein, and each local I/O line for driving is connected to a large number of memory cells. Then, a control circuit is connected to the large area writing driver 117 and the local writing drivers 120 to generate a block write signal and a normal write signal. The normal write data path is frozen by a block write control signal during the block write cycle, thereby the power consumption during the block write operation is saved.

公开(公告)号：JPH09204417A

公开(公告)日：1997-08-05

申请号：JP22655096

申请日：1996-08-28

Applicant: HYUNDAI ELECTRONICS AMERICA ,  OODEIAMU MAIKUROSHISUTEMUZU IN

Inventor： JIYUAN PINEEDA

IPC: G06F9/38 ,  G06F15/78 ,  G06F17/14 ,  H04N7/30

Abstract: PROBLEM TO BE SOLVED: To execute inverse discrete cosine transformation(IDCT) at high speed by multiplying a previous scaling coefficient to be changed according to the position of an input DCT coefficient in data to the coefficient on a 1st stage and performing multiplication due to a special IDCT coefficient matrix on a 2nd stage. SOLUTION: A multiplexer 104 sends DCT coefficient data to a matrix multiplier 106. In order to generate an intermediate output matrix, the multiplier 106 respectively multiplies the IDCT coefficient matrix to the respective rows of a DCT coefficient matrix. On an intermediate scaling/rounding stage 112, suitable bit precision is allocated to the intermediate output matrix, and the intermediate output matrix is transferred by a transfer buffer 114. The multiplexer 104 selects the intermediate matrix as the input to the multiplier 106. The multiplier 106 multiplies a T coefficient matrix to the intermediate output matrix for each row. On a stage 108, bit precision is allocated to the output matrix.