公开(公告)号：US5686735A

公开(公告)日：1997-11-11

申请号：US390357

申请日：1995-02-17

Applicant: Jai-hoon Sim

Inventor： Jai-hoon Sim

IPC: H01L29/78 ,  H01L21/336 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L27/1203 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78654

Abstract: An SOI transistor whose source region and/or drain region have a heterostructure made up of at least two different semiconductor materials, to thereby prevent a bipolar-induced breakdown.

Abstract translation: SOI晶体管，其源极区和/或漏极区具有由至少两个不同的半导体材料构成的异质结构，从而防止双相诱发击穿。

公开(公告)号：US5619467A

公开(公告)日：1997-04-08

申请号：US623790

申请日：1996-03-29

Applicant: Jai-Hoon Sim

Inventor： Jai-Hoon Sim

IPC: G11C11/419 ,  G11C7/06 ,  G11C11/409

CPC classification number: G11C7/062 ,  G11C2207/063

Abstract: A current sense amplifier circuit for a semiconductor memory device includes a differential amplifier which senses the signal currents input to first and second input nodes, amplifies the difference between the two signals and outputs the sense-amplified signals to first and second output nodes. A first feedback circuit is connected between the second input node and a current controlling node and has a controlling terminal connected to the first output node. A second feedback circuit is connected between the first input node and the current controlling node and has a controlling terminal connected to the second output node. By feeding back voltages from the counterpart output nodes through the cross-connected feedback circuits, the difference between low level input signals can be efficiently detected and a stable sense-amplified output is obtained.

Abstract translation: 用于半导体存储器件的电流检测放大器电路包括差分放大器，其感测输入到第一和第二输入节点的信号电流，放大两个信号之间的差，并将读出放大的信号输出到第一和第二输出节点。 第一反馈电路连接在第二输入节点和电流控制节点之间，并且具有连接到第一输出节点的控制终端。 第二反馈电路连接在第一输入节点和当前控制节点之间，并且具有连接到第二输出节点的控制终端。 通过交叉连接反馈电路从对方输出节点反馈电压，可以有效地检测低电平输入信号之间的差异，并获得稳定的读出放大输出。

公开(公告)号：US08467220B2

公开(公告)日：2013-06-18

申请号：US12856481

申请日：2010-08-13

Applicant: Jai Hoon Sim

Inventor： Jai Hoon Sim

IPC: G11C5/06 ,  G11C11/24 ,  H01L27/108

CPC classification number: H01L27/0207 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7827

Abstract: The present invention relates to a DRAM device having 4F2 size cells and a method for fabricating the same. The DRAM device comprises plural word lines arranged parallel to each other in one direction, plural bit lines arranged parallel to each other and in an intersecting manner with the word line, and plural memory cells having a transistor and a capacitor connected electrically to a source terminal of the transistor. A gate terminal of the transistor is filling an associated trench between two adjacent memory cells in a bit line direction and simultaneously covering a sidewall of said two adjacent memory cells via a gate insulating film interposed between the gate terminal and said two adjacent memory cells. An interval between the gate terminals in the bit or the word line direction, is more distant than 1F, and the F means minimal processing size.

Abstract translation: 本发明涉及具有4F2尺寸单元的DRAM器件及其制造方法。 DRAM装置包括在一个方向上彼此平行布置的多个字线，彼此平行并与字线交叉排列的多个位线，以及多个存储单元，具有晶体管和与源极端子电连接的电容器 的晶体管。 晶体管的栅极端子以位线方向填充两个相邻的存储单元之间的相关联的沟槽，并且经由插入在栅极端子和所述两个相邻存储器单元之间的栅极绝缘膜同时覆盖所述两个相邻存储单元的侧壁。 位或字线方向上的栅极端子之间的间隔比1F更远，F表示最小的处理尺寸。

公开(公告)号：US20120236620A1

公开(公告)日：2012-09-20

申请号：US13420505

申请日：2012-03-14

Applicant: Jai-Hoon Sim

Inventor： Jai-Hoon Sim

IPC: G11C5/06 ,  H01L21/762

CPC classification number: H01L27/228 ,  G11C5/063 ,  G11C11/1659 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2436

Abstract: The present invention relates to a nonvolatile memory device and a manufacturing method thereof, the device comprising a plurality of word lines; a plurality of bit lines perpendicular to the word lines; and a plurality of memory cells including a transistor with a source connected to a source line, a gate, and a drain connected to a memory element, with the other end of the memory element connected to the bit lines. Between memory cells adjacent along a bit line, a gate terminal in a groove between the memory cells connects the gates in the memory cells to a word line. Memory cells adjacent along a word line are connected to one bit line contact point, and memory cells sharing a gate terminal are connected to different bit lines. Bit lines are disposed at the upper portion and source lines at the lower end of the memory cell.

Abstract translation: 非易失性存储器件及其制造方法技术领域本发明涉及非易失性存储器件及其制造方法，该器件包括多个字线; 垂直于字线的多个位线; 以及多个存储单元，包括具有连接到源极线的源极，连接到存储元件的栅极和漏极的晶体管，存储元件的另一端连接到位线。 在沿着位线相邻的存储单元之间，存储单元之间的沟槽中的栅极端子将存储单元中的栅极连接到字线。 沿着字线相邻的存储单元连接到一个位线接触点，并且共享栅极端子的存储单元连接到不同的位线。 位线设置在存储单元下端的上部和源极线处。

公开(公告)号：US07977726B2

公开(公告)日：2011-07-12

申请号：US11896418

申请日：2007-08-31

Applicant: Jai-Hoon Sim

Inventor： Jai-Hoon Sim

IPC: H01L27/108

CPC classification number: H01L28/87 ,  H01L27/1085

Abstract: A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor. The cell capacitor includes a first, second and third dielectric layer, and a first, second and third capacitor electrode. The first dielectric layer is located on a first capacitor electrode. The second capacitor electrode is located on top of the first dielectric layer. The second dielectric layer is located on the second capacitor electrode. The third capacitor electrode is located on the second dielectric layer and is electrically connected with the drain. The third dielectric layer is located between the third capacitor electrode and the gate for isolating the gate from the third capacitor electrode.

Abstract translation: 提供了动态随机存取存储器（DRAM）单元及其制造方法。 DRAM单元包括单元晶体管和单元电容器。 电池电容器包括第一，第二和第三电介质层，以及第一，第二和第三电容器电极。 第一电介质层位于第一电容器电极上。 第二电容器电极位于第一电介质层的顶部。 第二电介质层位于第二电容器电极上。 第三电容器电极位于第二电介质层上并与漏极电连接。 第三电介质层位于第三电容器电极和栅极之间，用于将栅极与第三电容器电极隔离。