中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

825 records (took 0.024 seconds)

    METHOD OF FABRICATING A TRANSISTOR WITH SEMICONDUCTOR GATE COMBINED LOCALLY WITH A METAL
    21.
    发明申请
    METHOD OF FABRICATING A TRANSISTOR WITH SEMICONDUCTOR GATE COMBINED LOCALLY WITH A METAL 审中-公开
    制造半导体门与金属组合的晶体管的方法

    公开(公告)号：WO2008084085A9

    公开(公告)日：2009-09-03

    申请号：PCT/EP2008050260

    申请日：2008-01-10

    Applicant: ST MICROELECTRONICS CROLLES 2 ,  NXP BV ,  MUELLER MARKUS ,  BIDAL GREGORY

    Inventor： MUELLER MARKUS ,  BIDAL GREGORY

    IPC: H01L21/28

    CPC classification number: H01L29/517 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/28105 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

    Abstract: The invention concerns a method of forming a field effect transistor comprising a gate (G) formed on an insulating layer, the gate having, in a zone in contact with the insulating layer, a semiconducting central zone (50) and lateral zones (48) in the length of the gate (G), the method comprising forming a gate (G) comprising a portion of insulating layer (32), a portion of semiconducting layer formed over the insulating layer (32), and a portion of mask layer formed over the semiconducting layer; performing an etching of the portion of the mask layer such that only a portion in the centre of the gate (G) remains; and reacting the semiconducting gate with a metal deposited over the gate.

    Abstract translation: 本发明涉及一种形成场效应晶体管的方法，该场效应晶体管包括形成在绝缘层上的栅极（G），该栅极在与绝缘层接触的区域内具有半导体中心区域（50）和侧向区域（48） 在栅极（G）的长度上，所述方法包括形成包括绝缘层（32）的一部分的栅极（G），形成在绝缘层（32）上的半导体层的一部分，以及形成的掩模层的一部分 在半导体层上; 对掩模层的部分进行蚀刻，使得只有栅极（G）的中心部分保留; 并使半导电栅极与沉积在栅极上的金属反应。

    IMPROVED MANUFACTURING METHOD FOR PLANAR INDEPENDENT-GATE OR GATE-ALL-AROUND TRANSISTORS
    22.
    发明申请
    IMPROVED MANUFACTURING METHOD FOR PLANAR INDEPENDENT-GATE OR GATE-ALL-AROUND TRANSISTORS 审中-公开
    用于平面独立门或门控绕线晶体管的改进制造方法

    公开(公告)号：WO2009081345A1

    公开(公告)日：2009-07-02

    申请号：PCT/IB2008/055418

    申请日：2008-12-18

    Applicant: NXP B.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  POUYDEBASQUE, Arnaud ,  CORONEL, Philippe ,  DENORME, Stephane

    Inventor： POUYDEBASQUE, Arnaud ,  CORONEL, Philippe ,  DENORME, Stephane

    IPC: H01L21/336 ,  H01L29/78

    CPC classification number: H01L29/66772 ,  H01L29/42392 ,  H01L29/66484 ,  H01L29/66636 ,  H01L29/7831 ,  H01L29/78654

    Abstract: The present invention relates to a method for fabricating a planar independent- double-gate FET or a planar gate-all-around FET on a bulk semiconductor substrate. The method comprises refilling a surface recess in an active semiconductor region with a buried sacrificial layer, and, after preparing a pre-processing a gate stack by respective deposition and patterning, the formation of a recess in the isolation regions so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that allows removing the buried sacrificial layer and so as to cause the recess to undercut portions of gate stack in the channel direction.

    Abstract translation: 本发明涉及在体半导体衬底上制造平面独立双栅极FET或平面栅极全周围FET的方法。 该方法包括在有源半导体区域中用掩埋牺牲层重新填充表面凹槽，并且在通过相应的沉积和图案化准备预处理栅极堆叠之后，在隔离区域中形成凹槽，以便使凹部 在指向内衬底的深度方向上延伸到允许去除掩埋牺牲层的深度水平，并且使得凹槽在通道方向上削弱栅极堆叠的部分。

    HIGH-STABILITY THIN-FILM CAPACITOR AND METHOD FOR MAKING THE SAME
    23.
    发明申请
    HIGH-STABILITY THIN-FILM CAPACITOR AND METHOD FOR MAKING THE SAME 审中-公开
    高稳定性薄膜电容器及其制造方法

    公开(公告)号：WO2008047000A3

    公开(公告)日：2008-06-19

    申请号：PCT/FR2007001701

    申请日：2007-10-16

    Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS CROLLES 2 ,  DEFAY EMMANUEL ,  GUILLAN JULIE ,  BLONKOWSKI SERGE

    Inventor： DEFAY EMMANUEL ,  GUILLAN JULIE ,  BLONKOWSKI SERGE

    IPC: H01G4/10 ,  H01G4/06 ,  H01G4/33

    CPC classification number: H01G4/1218 ,  H01G4/1254 ,  H01G4/33 ,  H01L27/016 ,  H01L28/40 ,  H01L28/56

    Abstract: According to the invention, the dielectric (6) of a capacitor (1) is made by superimposing at least two thin layers (6a, 6b) made of the same metallic oxide respectively in crystalline and amorphous forms and respectively having relative capacity quadratic ratios according to the opposed-signs voltage. The respective thickness d a and d c of the amorphous (6b) and crystalline (6a) thin layers correspond to the following general formulae in which: e 0 is the vacuum permittivity, e c and e a correspond to the relative permittivity of the metallic oxide respectively in the crystalline and amorphous forms, C s0 is the zero-field total surface capacity, and ? c et ? a correspond to the relative capacity quadratic ratios according to the electric field of the metallic oxide respectively in the crystalline form and in the amorphous form.

    Abstract translation: 根据本发明，电容器（1）的电介质（6）通过将由相同金属氧化物制成的至少两个薄层（6a，6b）分别叠加在晶体和非晶形中并分别具有相对容量二次比 到相反的电压。 非晶（6b）和结晶（6a）薄层的相应厚度d a a和d c c对应于以下通式，其中：e < / SUB>是真空介电常数，e和c分别对应于结晶和无定形形式的金属氧化物的相对介电常数，C < / SUB>是零场总表面容量，α3和α3分别对应于分别在金属氧化物的电场中的相对容量二次比 结晶形式和无定形形式。

    METHOD OF REDUCING RISK OF DELAMINATION OF A LAYER OF A SEMICONDUCTOR DEVICE
    24.
    发明申请
    METHOD OF REDUCING RISK OF DELAMINATION OF A LAYER OF A SEMICONDUCTOR DEVICE 审中-公开
    降低半导体器件层的分层风险的方法

    公开(公告)号：WO2007107176A1

    公开(公告)日：2007-09-27

    申请号：PCT/EP2006/004034

    申请日：2006-03-17

    Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  COOPER, Kevin ,  KORDIC, Srdjan ,  RIVOIRE, Maurice

    Inventor： COOPER, Kevin ,  KORDIC, Srdjan ,  RIVOIRE, Maurice

    IPC: H01L21/3105 ,  B24B37/04 ,  B24D17/00 ,  H01L21/304

    CPC classification number: H01L21/3105 ,  B24B9/065 ,  B24B37/042 ,  H01L21/304

    Abstract: A method of minimizing de lamination of a layer (14, 16, or 18), the method includes providing a semiconductor substrate (12), forming a first layer (14) over the semiconductor substrate, wherein the first layer has a first corner (20) and the first corner has a first angle of approximately 90 degrees; forming a second layer (16) over the first layer, wherein the second layer has a second corner (20) and the second corner has a second angle of approximately 90 degrees, and modifying the first and second corners to form a first slanted edge (50, 60, or 70) of the first layer and a second slanted edge (50, 60, or 70) of the second layer, wherein the first slanted edge and the second slanted edge are continuous with each other and the first slanted edge forms a third angle with respect to the semiconductor substrate, wherein the third angle is less than 30 degrees.

    Abstract translation: 一种使层（14,16或18）的层叠最小化的方法，所述方法包括提供半导体衬底（12），在所述半导体衬底上形成第一层（14），其中所述第一层具有第一角（ 20），并且第一角具有大约90度的第一角度; 在所述第一层上形成第二层（16），其中所述第二层具有第二角（20），并且所述第二角具有大约90度的第二角度，并且修改所述第一和第二角以形成第一倾斜边缘 50,60或70）和所述第二层的第二倾斜边缘（50,60或70），其中所述第一倾斜边缘和所述第二倾斜边缘彼此连续并且所述第一倾斜边缘形成 相对于半导体衬底的第三角度，其中第三角度小于30度。

    FABRICATION OF A DIFFUSION BARRIER CAP ON COPPER CONTAINING CONDUCTIVE ELEMENTS
    28.
    发明申请
    FABRICATION OF A DIFFUSION BARRIER CAP ON COPPER CONTAINING CONDUCTIVE ELEMENTS 审中-公开
    包含导电元件的扩散阻挡层的制造

    公开(公告)号：WO2008065125A1

    公开(公告)日：2008-06-05

    申请号：PCT/EP2007/062905

    申请日：2007-11-27

    Applicant: NXP B.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  TORRES, Joaquin ,  GOSSET, Laurent ,  ARNAL, Vincent ,  CHHUN, Sonarith

    Inventor： TORRES, Joaquin ,  GOSSET, Laurent ,  ARNAL, Vincent ,  CHHUN, Sonarith

    IPC: H01L21/768 ,  H01L21/321 ,  H01L23/532

    CPC classification number: H01L21/76849 ,  H01L21/7682 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for fabricating a self-aligned diffusion-barrier cap on a Cu- containing conductive element in an integrated-circuit device comprises: - providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface; - depositing a metal layer on the exposed surface of conductive element; - inducing diffusion of metal from the metal layer into a top section of the conductive element; - removing the remaining metal layer; - letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved.

    Abstract translation: 一种用于在集成电路器件中的含Cu导电元件上制造自对准扩散阻挡帽的方法包括： - 提供具有横向插入电介质层并具有暴露表面的含Cu导电元件的衬底; - 在导电元件的暴露表面上沉积金属层; - 诱导金属从金属层扩散到导电元件的顶部; - 去除剩余的金属层; - 使导电元件的顶部中的扩散金属和第二组分的颗粒彼此反应，以便构成覆盖导电元件的化合物。 选择金属层和第二组分的金属，使得该化合物形成抵抗Cu扩散的扩散阻挡层。 实现了集成电路器件的互连叠层中介电材料的介电常数的降低。

    CuSiN/SiN DIFFUSION BARRIER FOR COPPER IN INTEGRATED-CIRCUIT DEVICES
    29.
    发明申请
    CuSiN/SiN DIFFUSION BARRIER FOR COPPER IN INTEGRATED-CIRCUIT DEVICES 审中-公开
    用于集成电路设备中铜的CuSiN / SiN扩散阻挡层

    公开(公告)号：WO2008028850A1

    公开(公告)日：2008-03-13

    申请号：PCT/EP2007/058998

    申请日：2007-08-29

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  JOURDAN, Nicolas ,  GOSSET, Laurant Georges ,  TORRES, Joaquin

    Inventor： JOURDAN, Nicolas ,  GOSSET, Laurant Georges ,  TORRES, Joaquin

    IPC: H01L21/768 ,  H01L23/532

    CPC classification number: H01L21/76831 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present invention relates to an integrated-circuit device that has at least one Copper-containing feature in a dielectric layer, and a diffusion-barrier layer stack arranged between the feature and the dielectric layer. The integrated-circuit device of the invention has a diffusion-barrier layer stack, which comprises, in a direction from the Copper-containing feature to the dielectric layer, a CuSiN layer and a SiN layer. This layer combinat ion provides an efficient barrier for suppressing Copper diffusion from the feature into the dielectric layer. Furthermore, a CuSiN/SiN layer sequence provides an improved adhesion between the layers of the diffusion-barrier layer stack and the dielectric layer, and thus improves the electromigration performance of the integrated-circuit device during operation. Therefore, the reliability of device operation and the lifetime of the integrate- circuit device are improved in comparison with prior-art devices. The invention further relates to a method for fabricating such an integrated-circuit device.

    Abstract translation: 本发明涉及在电介质层中具有至少一个含铜特征的集成电路器件，以及布置在该特征与该介电层之间的扩散阻挡层堆叠。 本发明的集成电路器件具有扩散阻挡层堆叠，其包括在从含铜特征到电介质层的方向上具有CuSiN层和SiN层。 该层组合离子提供了有效的屏障，用于抑制从特征进入电介质层的铜扩散。 此外，CuSiN / SiN层序列提供了扩散阻挡层堆叠层和电介质层之间的改进的粘合性，从而提高了集成电路器件在操作期间的电迁移性能。 因此，与现有技术的器件相比，器件操作的可靠性和集成电路器件的寿命得到改善。 本发明还涉及一种用于制造这种集成电路器件的方法。

    NOVEL HARD MASK STRUCTURE FOR PATTERNING FEATURES IN SEMICONDUCTOR DEVICES
    30.
    发明申请
    NOVEL HARD MASK STRUCTURE FOR PATTERNING FEATURES IN SEMICONDUCTOR DEVICES 审中-公开
    用于在半导体器件中绘制特征的新型硬掩模结构

    公开(公告)号：WO2008015212A1

    公开(公告)日：2008-02-07

    申请号：PCT/EP2007/057899

    申请日：2007-07-31

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  BROEKAART, Marcel, Eduard, Irene ,  DE-JONGHE, Veronique ,  LEVERD, François

    Inventor： BROEKAART, Marcel, Eduard, Irene ,  DE-JONGHE, Veronique ,  LEVERD, François

    IPC: H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213

    CPC classification number: H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139

    Abstract: The present invention relates to a method for fabricating at least one feature, which has a target lateral width, in a substrate layer. The method allows fabricating a feature with a target lateral width in a substrate layer that is smaller than can be obtained with the used lithographic equipment. In comparison with known methods, it provides an increased resistance to temperatures typically used during processing, in particular, during a plasma etching step. The increased temperature resistance is achieved by using a layer structure that comprises an amorphous carbon layer on the substrate layer, a capping layer on the amorphous carbon layer, and a first resist layer structure on the capping layer. In this layer structure, a carbon contribution to the etching process, which is usually provided by a resist material, is provided by the amorphous carbon layer, which forms a hard mask on the substrate layer.

    Abstract translation: 本发明涉及在衬底层中制造具有目标横向宽度的至少一个特征的方法。 该方法允许制造在衬底层中具有小于可以使用所使用的光刻设备获得的目标横向宽度的特征。 与已知的方法相比，它提供了对加工期间通常使用的温度的增加的抗性，特别是在等离子体蚀刻步骤期间。 通过使用在基底层上包含无定形碳层，无定形碳层上的覆盖层和覆盖层上的第一抗蚀剂层结构的层结构来实现提高的耐温性。 在该层结构中，通常由抗蚀剂材料提供的对蚀刻工艺的碳贡献由在基底层上形成硬掩模的无定形碳层提供。

Patent Agency Ranking