公开(公告)号：WO2007137049A3

公开(公告)日：2008-01-31

申请号：PCT/US2007069002

申请日：2007-05-16

Applicant: IBM ,  BERNSTEIN KERRY ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  JAFFE MARK DAVID ,  KARTSCHOKE PAUL DAVID ,  LUCE STEPHEN ELLINWOOD ,  STAMPER ANTHONY KENDALL

Inventor： BERNSTEIN KERRY ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  JAFFE MARK DAVID ,  KARTSCHOKE PAUL DAVID ,  LUCE STEPHEN ELLINWOOD ,  STAMPER ANTHONY KENDALL

IPC: H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5329 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon (110A and 110B) from two silicon-on- insulator wafers (110A and 100B), respectively, having devices (130A and 130B), respectively, fabricated therein and bonding them back to back utilizing the buried oxide layers (115). Contacts (210) are then formed in the upper wafer (I00B) to devices (130A) in the lower wafer (100A) and wiring levels (170) are formed on the upper wafer (100B). The lower wafer (100A) may include wiring levels (170). The lower wafer (100A) may include landing pads (230) for the contacts. Contacts to the silicon layer (120) of the lower wafer (100A) may be silicided.

Abstract translation: 一种半导体结构及其制造方法。 该方法包括从分别制造在其中的器件（130A和130B）的两个绝缘体上硅晶片（110A和100​​B）去除后侧硅（110A和110B），并使用掩埋氧化物 层（115）。 接触件（210）然后在上晶片（I00B）中形成在下晶片（100A）中的器件（130A），并且布线层（170）形成在上晶片（100B）上。 下晶片（100A）可以包括布线​​层（170）。 下晶片（100A）可以包括用于触点的着陆焊盘（230）。 与下晶片（100A）的硅层（120）的接触可以被硅化。

公开(公告)号：WO2007131867A1

公开(公告)日：2007-11-22

申请号：PCT/EP2007/054077

申请日：2007-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  JAFFE, Mark, David ,  DALTON, Timothy, Joseph ,  GAMBINO, Jeffrey, Peter ,  KARTSCHOKE, Paul, David ,  STAMPER, Anthony, Kendall ,  BERNSTEIN, Kerry

Inventor： JAFFE, Mark, David ,  DALTON, Timothy, Joseph ,  GAMBINO, Jeffrey, Peter ,  KARTSCHOKE, Paul, David ,  STAMPER, Anthony, Kendall ,  BERNSTEIN, Kerry

IPC: H01L21/768 ,  H01L27/12

CPC classification number: H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Abstract translation: 具有相对侧的布线电平的半导体器件以及制造与相对侧的器件和布线电平接触的半导体结构的方法。 该方法包括在绝缘体上硅衬底上制造器件，其中器件的第一触点和第一侧上的器件和布线电平到第一触点，去除下硅层以露出掩埋氧化物层，形成第二触点到器件 通过掩埋氧化物层并在掩埋氧化物层上形成布线层到第二触点。

公开(公告)号：WO2004114395A3

公开(公告)日：2004-12-29

申请号：PCT/EP2004/051046

申请日：2004-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  GAMBINO, Jeffrey ,  COONEY, Edward, III ,  STAMPER, Anthony ,  MOTSIFF, Thomas ,  LANE, Michael ,  SIMON, Andrew

Inventor： GAMBINO, Jeffrey ,  COONEY, Edward, III ,  STAMPER, Anthony ,  MOTSIFF, Thomas ,  LANE, Michael ,  SIMON, Andrew

IPC: H01L21/768

Abstract: Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

公开(公告)号：WO2004114395A2

公开(公告)日：2004-12-29

申请号：PCT/EP2004/051046

申请日：2004-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  GAMBINO, Jeffrey ,  COONEY, Edward, III ,  STAMPER, Anthony ,  MOTSIFF, Thomas ,  LANE, Michael ,  SIMON, Andrew

Inventor： GAMBINO, Jeffrey ,  COONEY, Edward, III ,  STAMPER, Anthony ,  MOTSIFF, Thomas ,  LANE, Michael ,  SIMON, Andrew

IPC: H01L21/768

CPC classification number: H01L21/76811 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

Abstract translation: 公开了用于形成双镶嵌后端（BEOL）互连结构的方法，其使用与用于线路导体的那些不同的通孔或螺柱的材料，或者使用不同于所使用的通孔衬垫的材料 用于沟槽衬垫，或者具有不同于沟槽衬套的通孔衬垫厚度。 优选地，在通孔中使用厚的难熔金属以改善机械强度，同时仅在沟槽中使用薄的难熔金属来提供低电阻。

公开(公告)号：WO2013070294A1

公开(公告)日：2013-05-16

申请号：PCT/US2012/050743

申请日：2012-08-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  HARAME, David, L. ,  STAMPER, Anthony, K.

Inventor： HARAME, David, L. ,  STAMPER, Anthony, K.

IPC: H03H9/54

CPC classification number: B81B3/0027 ,  B81B2201/0285 ,  H01L21/84 ,  H01L27/1203 ,  H01L41/1136 ,  H01L2224/73265 ,  H03H3/02 ,  H03H9/1007 ,  H03H9/173 ,  H03H2001/0064 ,  H03H2003/027 ,  H03H2009/155 ,  H03H2009/241

Abstract: Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, methods of manufacture and design structure are provided. The method includes forming a single crystalline beam (18) from a silicon layer (14) on an insulator (12). The method further includes providing a coating of insulator material (22) over the single crystalline beam. The method further includes forming a via (34a) through the insulator material exposing a wafer (10) underlying the insulator. The insulator material remains over the single crystalline beam. The method further includes providing a sacrificial material (36) in the via and over the insulator material. The method further includes providing a lid (38) on the sacrificial material. The method further includes venting, through the lid, the sacrificial material and a portion of the wafer under the single crystalline beam to form an upper cavity (42a) above the single crystalline beam and a lower cavity (42b) in the wafer, below the single crystalline beam.

Abstract translation: 提供了与CMOS器件集成的体声波滤波器和/或体声波谐振器，制造方法和设计结构。 该方法包括从绝缘体（12）上的硅层（14）形成单晶束（18）。 该方法还包括在单晶束上提供绝缘体材料（22）的涂层。 该方法还包括通过暴露出绝缘体下方的晶片（10）的绝缘体材料形成通孔（34a）。 绝缘体材料保留在单晶束上。 该方法还包括在通孔和绝缘体材料上提供牺牲材料（36）。 该方法还包括在牺牲材料上提供盖（38）。 该方法还包括在单结晶体束下通过盖子将牺牲材料和晶片的一部分排出，以在晶片上方形成上空腔（42a），并在晶片的下方形成下空腔（42b） 单晶束。

公开(公告)号：WO2012177371A1

公开(公告)日：2012-12-27

申请号：PCT/US2012/040339

申请日：2012-06-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  JAHNES, Christopher, V. ,  STAMPER, Anthony, K.

Inventor： JAHNES, Christopher, V. ,  STAMPER, Anthony, K.

IPC: H01L29/84

CPC classification number: B81B3/001 ,  B81B3/0021 ,  B81B3/0059 ,  B81B3/0072 ,  B81B7/0006 ,  B81B7/008 ,  B81B2201/016 ,  B81B2203/0163 ,  B81C1/00015 ,  B81C1/0015 ,  B81C1/00476 ,  G06F17/5045 ,  H01L41/094 ,  H01L41/1134 ,  H01L41/1138 ,  Y10T29/49002 ,  Y10T29/49005 ,  Y10T29/4908 ,  Y10T29/49121

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are provided. The method of forming a MEMS structure includes forming a wiring layer (14) on a substrate (10) comprising actuator electrodes (115) and a contact electrode (110). The method further includes forming a MEMS beam (100) above the wiring layer (14). The method further includes forming at least one spring (200) attached to at least one end of the MEMS beam (100). The method further includes forming an array of mini -bumps (105') between the wiring layer (14) and the MEMS beam (100).

Abstract translation: 提供微机电系统（MEMS）结构，制造方法和设计结构。 形成MEMS结构的方法包括在包括致动器电极（115）和接触电极（110）的基板（10）上形成布线层（14）。 该方法还包括在布线层（14）上方形成MEMS光束（100）。 该方法还包括形成附接到MEMS梁（100）的至少一端的至少一个弹簧（200）。 所述方法还包括在所述布线层（14）和所述MEMS光束（100）之间形成微型凸起（105'）的阵列。

公开(公告)号：WO2011090852A3

公开(公告)日：2011-07-28

申请号：PCT/US2011/020913

申请日：2011-01-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  HERRIN, Russell, T. ,  LINDGREN, Peter, J. ,  SPROGIS, Edmund, J. ,  STAMPER, Anthony, K.

Inventor： HERRIN, Russell, T. ,  LINDGREN, Peter, J. ,  SPROGIS, Edmund, J. ,  STAMPER, Anthony, K.

IPC: H01L21/768

Abstract: A method of manufacturing an integrated circuit structure forms a first opening in a substrate (100; Figure 1) and lines the first opening with a protective liner. (102) The method deposits a material into the first opening (104) and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. (108) The method removes the material from the first opening through the second opening in the protective material. (110) The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.

公开(公告)号：WO2010015678A3

公开(公告)日：2010-10-28

申请号：PCT/EP2009060213

申请日：2009-08-06

Applicant: IBM ,  IBM UK ,  STAMPER ANTHONY ,  ANDERSON FELIX PATRICK ,  MCDEVITT THOMAS LEDDY ,  EDELSTEIN DANIEL ,  COTE WILLIAM

Inventor： STAMPER ANTHONY ,  ANDERSON FELIX PATRICK ,  MCDEVITT THOMAS LEDDY ,  EDELSTEIN DANIEL ,  COTE WILLIAM

IPC: H01L23/532 ,  H01L21/3105 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L24/13 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2221/1036 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/45147 ,  H01L2224/48847 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01006

Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion (12) thereof devoid of a fluorine boundary layer. The structure further includes a copper wire (20) in the trench having at least a bottom portion thereof in contact with the non- fluoride boundary layer (12) of the trench. A lead free solder bump (34) is in electrical contact with the copper wire (20).

Abstract translation: 具有改善的焊料凸点连接的结构和制造这种结构的方法在本文中提供。 该结构包括形成在电介质层中的沟槽，该沟槽至少具有一部分（12）缺少氟边界层。 该结构还包括在沟槽中的铜线（20），其至少其底部与沟槽的非氟化物边界层（12）接触。 无铅焊料凸块（34）与铜线（20）电接触。

公开(公告)号：WO2010015678A2

公开(公告)日：2010-02-11

申请号：PCT/EP2009/060213

申请日：2009-08-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  STAMPER, Anthony ,  ANDERSON, Felix, Patrick ,  MCDEVITT, Thomas, Leddy ,  EDELSTEIN, Daniel ,  COTE, William

Inventor： STAMPER, Anthony ,  ANDERSON, Felix, Patrick ,  MCDEVITT, Thomas, Leddy ,  EDELSTEIN, Daniel ,  COTE, William

IPC: H01L23/532 ,  H01L23/485 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/60

CPC classification number: H01L24/13 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2221/1036 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/45147 ,  H01L2224/48847 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01006

Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non- fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

Abstract translation: 具有改善的焊料凸点连接的结构和制造这种结构的方法在本文中提供。 该结构包括在至少一部分没有氟边界层的电介质层中形成的沟槽。 该结构还包括在沟槽中的铜线，其至少其底部与沟槽的非氟化物边界层接触。 无铅焊料凸块与铜线电接触。

公开(公告)号：WO2007084982A8

公开(公告)日：2008-07-10

申请号：PCT/US2007060767

申请日：2007-01-19

Applicant: IBM ,  COOLBAUGH DOUGLAS D ,  DOWNES KEITH E ,  LINDGREN PETER J ,  STAMPER ANTHONY K

Inventor： COOLBAUGH DOUGLAS D ,  DOWNES KEITH E ,  LINDGREN PETER J ,  STAMPER ANTHONY K

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76832 ,  H01L23/5223 ,  H01L28/60 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and semiconductor device. In the method, at least one partial via (26) is etched in a stacked structure and a border (32) is formed about the at least one partial via (26). The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer (22).

Abstract translation: 一种方法和半导体器件。 在该方法中，至少一个部分通孔（26）以堆叠结构被蚀刻，并且围绕至少一个部分通孔（26）形成边界（32）。 该方法还包括使用选择性蚀刻执行厚布线，同时继续蚀刻至少一个蚀刻停止层（22）。