公开(公告)号：WO2007137049A3

公开(公告)日：2008-01-31

申请号：PCT/US2007069002

申请日：2007-05-16

Applicant: IBM ,  BERNSTEIN KERRY ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  JAFFE MARK DAVID ,  KARTSCHOKE PAUL DAVID ,  LUCE STEPHEN ELLINWOOD ,  STAMPER ANTHONY KENDALL

Inventor： BERNSTEIN KERRY ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  JAFFE MARK DAVID ,  KARTSCHOKE PAUL DAVID ,  LUCE STEPHEN ELLINWOOD ,  STAMPER ANTHONY KENDALL

IPC: H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5329 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon (110A and 110B) from two silicon-on- insulator wafers (110A and 100B), respectively, having devices (130A and 130B), respectively, fabricated therein and bonding them back to back utilizing the buried oxide layers (115). Contacts (210) are then formed in the upper wafer (I00B) to devices (130A) in the lower wafer (100A) and wiring levels (170) are formed on the upper wafer (100B). The lower wafer (100A) may include wiring levels (170). The lower wafer (100A) may include landing pads (230) for the contacts. Contacts to the silicon layer (120) of the lower wafer (100A) may be silicided.

Abstract translation: 一种半导体结构及其制造方法。 该方法包括从分别制造在其中的器件（130A和130B）的两个绝缘体上硅晶片（110A和100​​B）去除后侧硅（110A和110B），并使用掩埋氧化物 层（115）。 接触件（210）然后在上晶片（I00B）中形成在下晶片（100A）中的器件（130A），并且布线层（170）形成在上晶片（100B）上。 下晶片（100A）可以包括布线​​层（170）。 下晶片（100A）可以包括用于触点的着陆焊盘（230）。 与下晶片（100A）的硅层（120）的接触可以被硅化。

公开(公告)号：WO2007131867A1

公开(公告)日：2007-11-22

申请号：PCT/EP2007/054077

申请日：2007-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  JAFFE, Mark, David ,  DALTON, Timothy, Joseph ,  GAMBINO, Jeffrey, Peter ,  KARTSCHOKE, Paul, David ,  STAMPER, Anthony, Kendall ,  BERNSTEIN, Kerry

Inventor： JAFFE, Mark, David ,  DALTON, Timothy, Joseph ,  GAMBINO, Jeffrey, Peter ,  KARTSCHOKE, Paul, David ,  STAMPER, Anthony, Kendall ,  BERNSTEIN, Kerry

IPC: H01L21/768 ,  H01L27/12

CPC classification number: H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Abstract translation: 具有相对侧的布线电平的半导体器件以及制造与相对侧的器件和布线电平接触的半导体结构的方法。 该方法包括在绝缘体上硅衬底上制造器件，其中器件的第一触点和第一侧上的器件和布线电平到第一触点，去除下硅层以露出掩埋氧化物层，形成第二触点到器件 通过掩埋氧化物层并在掩埋氧化物层上形成布线层到第二触点。

公开(公告)号：WO2007137969A1

公开(公告)日：2007-12-06

申请号：PCT/EP2007/054941

申请日：2007-05-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  CLEVENGER, Lawrence ,  DALTON, Timothy, Joseph ,  HSU, Louis, Lu-Chen ,  RADENS, Carl, John ,  RAMACHANDRAN, Vidhya ,  WONG, Keith, Kwong Hon ,  YANG, Chih-Chao

Inventor： CLEVENGER, Lawrence ,  DALTON, Timothy, Joseph ,  HSU, Louis, Lu-Chen ,  RADENS, Carl, John ,  RAMACHANDRAN, Vidhya ,  WONG, Keith, Kwong Hon ,  YANG, Chih-Chao

IPC: H01L21/8242 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

Abstract: Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semico nductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.

Abstract translation: 提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。 在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。 在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

公开(公告)号：WO2007131867B1

公开(公告)日：2008-03-06

申请号：PCT/EP2007054077

申请日：2007-04-25

Applicant: IBM ,  IBM UK ,  JAFFE MARK DAVID ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  KARTSCHOKE PAUL DAVID ,  STAMPER ANTHONY KENDALL ,  BERNSTEIN KERRY

Inventor： JAFFE MARK DAVID ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  KARTSCHOKE PAUL DAVID ,  STAMPER ANTHONY KENDALL ,  BERNSTEIN KERRY

IPC: H01L21/768 ,  H01L27/12

CPC classification number: H01L21/76898 ,  H01L21/768 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Abstract translation: 具有相对侧的布线电平的半导体器件以及制造与相对侧的器件和布线电平接触的半导体结构的方法。 该方法包括在绝缘体上硅衬底上制造器件，其中器件的第一接触和第一侧的第一接触处的布线电平，去除下硅层以暴露所述掩埋氧化物层，形成第二触点到器件 通过掩埋氧化物层形成掩埋氧化物层上方的布线电平到第二触点。

公开(公告)号：WO2007137049A2

公开(公告)日：2007-11-29

申请号：PCT/US2007/069002

申请日：2007-05-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BERNSTEIN, Kerry ,  DALTON, Timothy, Joseph ,  GAMBINO, Jeffrey, Peter ,  JAFFE, Mark, David ,  KARTSCHOKE, Paul, David ,  LUCE, Stephen, Ellinwood ,  STAMPER, Anthony, Kendall

Inventor： BERNSTEIN, Kerry ,  DALTON, Timothy, Joseph ,  GAMBINO, Jeffrey, Peter ,  JAFFE, Mark, David ,  KARTSCHOKE, Paul, David ,  LUCE, Stephen, Ellinwood ,  STAMPER, Anthony, Kendall

IPC: H01L23/52 ,  H01L21/44

CPC classification number: H01L25/0657 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5329 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon (110A and 110B) from two silicon-on- insulator wafers (110A and 100B), respectively, having devices (130A and 130B), respectively, fabricated therein and bonding them back to back utilizing the buried oxide layers (115). Contacts (210) are then formed in the upper wafer (I00B) to devices (130A) in the lower wafer (100A) and wiring levels (170) are formed on the upper wafer (100B). The lower wafer (100A) may include wiring levels (170). The lower wafer (100A) may include landing pads (230) for the contacts. Contacts to the silicon layer (120) of the lower wafer (100A) may be silicided.

Abstract translation: 一种半导体结构及其制造方法。 该方法包括从分别制造在其中的器件（130A和130B）的两个绝缘体上硅晶片（110A和100​​B）去除后侧硅（110A和110B），并使用掩埋氧化物 层（115）。 接触件（210）然后在上晶片（I00B）中形成到下晶片（100A）中的器件（130A），并且布线级（170）形成在上晶片（100B）上。 下晶片（100A）可以包括布线​​层（170）。 下晶片（100A）可以包括用于触点的着陆焊盘（230）。 与下晶片（100A）的硅层（120）的接触可以被硅化。