公开(公告)号：WO2007143255A2

公开(公告)日：2007-12-13

申请号：PCT/US2007065030

申请日：2007-03-27

Applicant: MOTOROLA INC ,  STENGEL ROBERT E

Inventor： STENGEL ROBERT E

IPC: G06F9/44 ,  G06F9/45

CPC classification number: G06F1/025 ,  H03K5/131 ,  H03K2005/00045

Abstract: A signal generator consistent with certain embodiments of the invention has a reference clock (34) producing a periodic sequence of reference clock output pulses. A window generator (38) generates a plurality of time windows through which a selected plurality of the reference clock output pulses are selectively passed as windowed pulses so that the windowed pulses form a selected pattern of pulses. A programmable delay (46) has resolution of delay that has finer time granularity in delay than the period of the clock output pulses. The programmable delay (46) delays each of the windowed pulses by a programmed delay time to thereby provide a timing correction to the windowed pulses to produce an output pattern of pulses.

Abstract translation: 与本发明的某些实施例一致的信号发生器具有产生周期性参考时钟输出脉冲序列的参考时钟（34）。 窗口生成器（38）产生多个时间窗口，所选择的多个参考时钟输出脉冲通过该时间窗口被选择性地作为窗口脉冲通过，使得窗口脉冲形成选定的脉冲图案。 可编程延迟（46）具有延迟分辨率，延迟时间比时钟输出脉冲的周期更精细。 可编程延迟（46）将每个加窗脉冲延迟编程的延迟时间，从而为加窗脉冲提供定时校正以产生脉冲的输出模式。

公开(公告)号：WO2004114091A2

公开(公告)日：2004-12-29

申请号：PCT/US2004/019788

申请日：2004-06-18

Applicant: MOTOROLA, INC. ,  CAFARO, Nicholas, G. ,  STENGEL, Robert, E.

Inventor： CAFARO, Nicholas, G. ,  STENGEL, Robert, E.

IPC: G06F

CPC classification number: H03L7/0812 ,  G06F1/06

Abstract: A programmable skew clock signal generator has a frequency generator circuit (104) consistent with the invention produces an output signal F ϕ0 from a reference signal F ref A frequency accumulator (132, 152) is preloaded with a preload value P K1 and receives one reference signal cycle as a clock signal, receives a constant K 1 as an input thereto, with the frequency accumulator (132, 152) having a maximum count K MAX and producing an overflow output. A phase accumulator (136, 156) is preloaded with a preload value P C1 and receives one overflow cycle output from the frequency accumulator (132, 152) as a clock signal and receives a phase offset constant C 1 as an input thereto. The phase accumulator (136, 156) has a maximum count C MAX and produces a phase accumulator (136, 156) output. A delay line (320) is clocked by the reference signal F ref and produces a plurality of delayed reference clock signals at a plurality of tap outputs. A tap selecting circuit (140, 144; 160, 164) receives the phase accumulator output and selects at least one of the tap outputs in response thereto to produce an output F ϕ1 whose phase shift ϕ1 relative to F 0ϕ is a function of P K1 and P C1 .

Abstract translation: 可编程偏移时钟信号发生器具有与本发明一致的频率发生器电路（104），其从参考信号Fref A频率累加器（132,152）预加载有预加载值PK1并产生一个输出信号Fφ0，并且接收一个参考信号周期作为 时钟信号接收常数K1作为其输入，频率累加器（132,152）具有最大计数KMAX并产生溢出输出。 相位累加器（136,156）预加载有预载值PC1，并且从频率累加器（132,152）输出一个溢出周期作为时钟信号，并接收相位偏移常数C1作为其输入。 相位累加器（136,156）具有最大计数CMAX并产生输出相位累加器（136,156）。 延迟线（320）由参考信号Fref计时，并在多个抽头输出端产生多个延迟参考时钟信号。 抽头选择电路（140,144; 160,164）接收相位累加器输出，并响应于此选择抽头输出中的至少一个以产生相对于F0φ的相移φ1是PK1和PC1的函数的输出Fφ1。

公开(公告)号：WO2009073301A1

公开(公告)日：2009-06-11

申请号：PCT/US2008/082399

申请日：2008-11-05

Applicant: MOTOROLA, INC. ,  STENGEL, Robert E. ,  GRADISHAR, Thomas L. ,  MACHAN, Stephen T.

Inventor： STENGEL, Robert E. ,  GRADISHAR, Thomas L. ,  MACHAN, Stephen T.

IPC: H03L7/081 ,  H03L7/16 ,  H03K5/15

CPC classification number: H03L7/16 ,  H03K5/15013 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/087

Abstract: A frequency generator (100) takes a signal source (clock or carrier) (101) and generates a edge encoded direct digital modulated differential output signal (110). The differential signal (110) is applied to a frequency extension quadrature generator (FEQG) (112). The FEQG (112) includes a fractional differential wavelength delay locked loop (DLL) (280) and a frequency multiplier (240). The DLL(280) generates a control voltage (214) with which to control delays of the edge encoded modulation signal (110). A frequency extended quadrature function is applied to the periodic steady state input signal with edge encoded modulation (110), to provide the output signal set 113.

Abstract translation: 频率发生器（100）接收信号源（时钟或载波）（101）并产生边缘编码直接数字调制差分输出信号（110）。 差分信号（110）被施加到频率扩展正交发生器（FEQG）（112）。 FEQG（112）包括分数差分波长延迟锁定环（DLL）（280）和倍频器（240）。 DLL（280）产生用于控制边缘编码调制信号（110）的延迟的控制电压（214）。 频率扩展正交函数被施加到具有边缘编码调制（110）的周期性稳态输入信号，以提供输出信号组113。

公开(公告)号：WO2008042550A3

公开(公告)日：2008-11-13

申请号：PCT/US2007077819

申请日：2007-09-07

Applicant: MOTOROLA INC ,  THOMPSON BRUCE M ,  STENGEL ROBERT E

Inventor： THOMPSON BRUCE M ,  STENGEL ROBERT E

IPC: H03F3/45

CPC classification number: H03F3/4508 ,  H03F1/565 ,  H03F3/26 ,  H03F3/602 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2203/45394 ,  H03F2203/45731

Abstract: An apparatus and method for eliminating unwanted signal power dissipation in balanced amplifier circuits and for prohibiting unwanted signal power from appearing at the balanced amplifier load is presented. Load impedances to the amplifier power output transistors are maintained very low at unwanted frequencies, and are at an operational impedance level at the fundamental frequency. An impedance network control concept is presented, which may be either manually or automatically implemented.

Abstract translation: 提出了一种用于消除平衡放大器电路中的不需要的信号功率消耗并且用于禁止不需要的信号功率出现在平衡放大器负载的设备和方法。 放大器功率输出晶体管的负载阻抗在不需要的频率下保持非常低，并且在基频处于工作阻抗水平。 提出了阻抗网络控制概念，其可以手动或自动实施。

公开(公告)号：WO2008051699A1

公开(公告)日：2008-05-02

申请号：PCT/US2007/080664

申请日：2007-10-08

Applicant: MOTOROLA, INC. ,  CAFARO, Nicholas G. ,  STENGEL, Robert E.

Inventor： CAFARO, Nicholas G. ,  STENGEL, Robert E.

IPC: H04L7/00

CPC classification number: H04L7/0331 ,  H04L7/0012

Abstract: A system and method for clock data recovery for programming direct digital synthesizers is disclosed. A counter (410) is used to calculate a coarse measurement of the clock frequency of a received digital signal (102), and a tap delay line (606) is used to calculate a fine measurement of the clock frequency of the received digital signal. The coarse and fine measurements are used to calculate a value for programming a direct digital synthesizer to produce a clock signal that is an approximate replica of the clock frequency of the received digital signal (102).

Abstract translation: 公开了用于编程直接数字合成器的时钟数据恢复的系统和方法。 计数器（410）用于计算接收到的数字信号（102）的时钟频率的粗略测量，采用分接延迟线（606）来计算所接收的数字信号的时钟频率的精细测量。 粗略和精细测量用于计算用于编程直接数字合成器以产生作为接收数字信号（102）的时钟频率的近似副本的时钟信号的值。

公开(公告)号：WO2006121629B1

公开(公告)日：2007-08-16

申请号：PCT/US2006016048

申请日：2006-04-27

Applicant: MOTOROLA INC ,  THOMPSON BRUCE M ,  STENGEL ROBERT E

Inventor： THOMPSON BRUCE M ,  STENGEL ROBERT E

IPC: H03F3/60

CPC classification number: H03F3/605

Abstract: A system and a method for providing an input to a distributed power amplifying system are provided. In an embodiment, a distributed power amplifying system includes a plurality of amplifying sections (102, 104, 106, and 108) and a plurality of drivers (110, 112, 114, and 116). Each of the plurality of drivers receives a common transmit signal (118) and an individual control signal (120, 122, 124, and 126). Each of the plurality of drivers independently preconditions the common transmit signal, to provide a transmit output signal (128, 130, 132, and 134) to each of the plurality of amplifying sections. The common transmit signal provided to each of the plurality of drivers is preconditioned, based on the individual control signal.

Abstract translation: 提供了一种用于向分布式功率放大系统提供输入的系统和方法。 在一个实施例中，分布式功率放大系统包括多个放大部分（102,104,106和108）和多个驱动器（110,112,114和116）。 多个驱动器中的每一个接收公共发送信号（118）和单独控制信号（120,122,124和126）。 多个驱动器中的每一个独立地预处理公共发送信号，以向多个放大部件中的每一个提供发送输出信号（128,130,132和134）。 基于单独的控制信号对提供给多个驱动器中的每一个的公共发送信号进行预处理。

公开(公告)号：WO2007061523A2

公开(公告)日：2007-05-31

申请号：PCT/US2006/039626

申请日：2006-10-09

Applicant: MOTOROLA, INC. ,  THOMPSON, Bruce, M. ,  OOI, Leng, H. ,  STENGEL, Robert, E.

Inventor： THOMPSON, Bruce, M. ,  OOI, Leng, H. ,  STENGEL, Robert, E.

IPC: H04B1/04

CPC classification number: H04B1/0475

Abstract: A vector signal processor (80) can include a digital to time converter (DTC), an RF memory (RFM) or an electronically tunable transmission line (ETTL) (82), a mixer, or other phase shifter (70) for receiving an output of the DTC or the ETTL, and a controller for selectively controlling the harmonic processing of the DTC, RFM or the ETTL and the phase processing of the mixer. The vector signal processor can uncouple a relative phase of a fundamental signal with respect to harmonics of the fundamental signal. The vector signal processor uses selective phase processing of the fundamental signal and related harmonic components. In a specific embodiment, the vector signal processor cancels harmonics of the fundamental signal and more specifically can cancel a third harmonic of the fundamental signal.

Abstract translation: 矢量信号处理器（80）可以包括数字到时间转换器（DTC），RF存储器（RFM）或电子可调谐传输线（ETTL）（82），混频器或其他 用于接收DTC或ETTL的输出的移相器（70），以及用于选择性地控制DTC，RFM或ETTL的谐波处理和混频器的相位处理的控制器。 矢量信号处理器可以将基本信号的相对相位与基本信号的谐波解耦合。 矢量信号处理器使用基本信号和相关谐波分量的选择性相位处理。 在特定实施例中，矢量信号处理器消除基本信号的谐波，并且更具体地可以消除基本信号的三次谐波。

公开(公告)号：WO2006121629A2

公开(公告)日：2006-11-16

申请号：PCT/US2006016048

申请日：2006-04-27

Applicant: MOTOROLA INC ,  THOMPSON BRUCE M ,  STENGEL ROBERT E

Inventor： THOMPSON BRUCE M ,  STENGEL ROBERT E

IPC: H03F3/60

CPC classification number: H03F3/605

Abstract: A system and a method for providing an input to a distributed power amplifying system are provided. In an embodiment, a distributed power amplifying system includes a plurality of amplifying sections (102, 104, 106, and 108) and a plurality of drivers (110, 112, 114, and 116). Each of the plurality of drivers receives a common transmit signal (118) and an individual control signal (120, 122, 124, and 126). Each of the plurality of drivers independently preconditions the common transmit signal, to provide a transmit output signal (128, 130, 132, and 134) to each of the plurality of amplifying sections. The common transmit signal provided to each of the plurality of drivers is preconditioned, based on the individual control signal.

Abstract translation: 提供了一种用于向分布式功率放大系统提供输入的系统和方法。 在一个实施例中，分布式功率放大系统包括多个放大部分（102,104,106和108）和多个驱动器（110,112,114和116）。 多个驱动器中的每个驱动器接收公共发送信号（118）和单独的控制信号（120,122,124和126）。 所述多个驱动器中的每个驱动器独立地对所述公共发送信号进行预处理，以向所述多个放大部分中的每一个提供发送输出信号（128,130,132和134）。 提供给多个驱动器中的每一个的公共发送信号基于各个控制信号进行预处理。

公开(公告)号：WO2005072298A3

公开(公告)日：2006-08-24

申请号：PCT/US2005002138

申请日：2005-01-25

Applicant: MOTOROLA INC ,  TOMERLIN ANDREW T ,  STENGEL ROBERT E

Inventor： TOMERLIN ANDREW T ,  STENGEL ROBERT E

IPC: H03H11/26 ,  H03K5/00 ,  H03K5/13 ,  H03L7/08 ,  H03L7/081 ,  H03L7/16

CPC classification number: H03L7/0802 ,  H03K5/133 ,  H03K2005/00019 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/16

Abstract: A configurable circuit consistent with certain embodiments has a variable length delay line (10), the delay line (10) having an input (24) and having N delay elements (12, 14, 16, 18, , 20) to provide a plurality of N delayed outputs (T(0) through T(N)). The variable length delay line (10) also has a number of active delay elements determined by a program command. A configurable processing array (32) receives the delayed outputs from the active delay elements and secondary data (38). The configurable processing array has an array of configurable circuit elements (104, 130, 150). The configurable processing array is configured to process the delayed outputs and the secondary data (38) in a manner for which the invention is to be used. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract translation: 与某些实施例一致的可配置电路具有可变长度延迟线（10），延迟线（10）具有输入（24）并具有N个延迟元件（12,14,16,18，，20）以提供多个 的N个延迟输出（T（0）到T（N））。 可变长度延迟线（10）还具有由程序命令确定的多个有效延迟元件。 可配置处理阵列（32）从主动延迟元件和辅助数据（38）接收延迟的输出。 可配置处理阵列具有可配置电路元件（104,130,150）的阵列。 可配置处理阵列被配置为以将要使用本发明的方式处理延迟的输出和辅助数据（38）。 该摘要不被认为是限制性的，因为其它实施例可能偏离本摘要中描述的特征。

公开(公告)号：WO2006052416A2

公开(公告)日：2006-05-18

申请号：PCT/US2005/037858

申请日：2005-10-21

Applicant: MOTOROLA, INC. ,  CAFARO, Nicholas, G. ,  GRADISHAR, Thomas, L. ,  STENGEL, Robert, E.

Inventor： CAFARO, Nicholas, G. ,  GRADISHAR, Thomas, L. ,  STENGEL, Robert, E.

IPC: H04L7/00

CPC classification number: H04L7/0083 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00286 ,  H03L7/0812 ,  H04L7/0337

Abstract: A DPC (300) includes: a frequency source (310) for generating a clock signal; a delay line (320) for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device (330) for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices (500, 510, 520) and a combining network. A method for use in a DPC includes: receiving (400) a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting (410) at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating (420) an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.

Abstract translation: DPC（300）包括：频率源（310），用于生成时钟信号; 延迟线（320），用于接收时钟信号并在输出抽头产生相移时钟信号; 数字控制装置（330），用于产生控制信号; 以及用于产生输出信号的加窗和选择电路，其包括时序逻辑器件（500,510,520）和组合网络。 一种在DPC中使用的方法包括：基于标识延迟线上的第一输出抽头的期望输出信号来接收（400）控制信号; 基于所述控制信号，在所述延迟线上选择（410）至少两个输出抽头以接收至少两个不同的相移时钟信号; 以及基于所述控制信号和基本上为所述期望输出信号的接收到的相移时钟信号来生成（420）输出信号。