公开(公告)号：WO2008042550A2

公开(公告)日：2008-04-10

申请号：PCT/US2007/077819

申请日：2007-09-07

Applicant: MOTOROLA, INC. ,  THOMPSON, Bruce, M. ,  STENGEL, Robert, E.

Inventor： THOMPSON, Bruce, M. ,  STENGEL, Robert, E.

IPC: H03F3/45

CPC classification number: H03F3/4508 ,  H03F1/565 ,  H03F3/26 ,  H03F3/602 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2203/45394 ,  H03F2203/45731

Abstract: An apparatus and method for eliminating unwanted signal power dissipation in balanced amplifier circuits and for prohibiting unwanted signal power from appearing at the balanced amplifier load is presented. Load impedances to the amplifier power output transistors are maintained very low at unwanted frequencies, and are at an operational impedance level at the fundamental frequency. An impedance network control concept is presented, which may be either manually or automatically implemented.

Abstract translation: 提出了用于消除平衡放大器电路中不需要的信号功率耗散并且用于禁止在平衡放大器负载处出现不想要的信号功率的装置和方法。 放大器功率输出晶体管的负载阻抗在不需要的频率下保持非常低，并且在基频处于工作阻抗级。 提出了阻抗网络控制概念，可以手动或自动实现。

公开(公告)号：WO2007143255A3

公开(公告)日：2007-12-13

申请号：PCT/US2007/065030

申请日：2007-03-27

Applicant: MOTOROLA, INC. ,  STENGEL, Robert, E.

Inventor： STENGEL, Robert, E.

IPC: G06F1/02

Abstract: A signal generator consistent with certain embodiments of the invention has a reference clock (34) producing a periodic sequence of reference clock output pulses. A window generator (38) generates a plurality of time windows through which a selected plurality of the reference clock output pulses are selectively passed as windowed pulses so that the windowed pulses form a selected pattern of pulses. A programmable delay (46) has resolution of delay that has finer time granularity in delay than the period of the clock output pulses. The programmable delay (46) delays each of the windowed pulses by a programmed delay time to thereby provide a timing correction to the windowed pulses to produce an output pattern of pulses.

公开(公告)号：WO2006121629A3

公开(公告)日：2006-11-16

申请号：PCT/US2006/016048

申请日：2006-04-27

Applicant: MOTOROLA, INC. ,  THOMPSON, Bruce, M. ,  STENGEL, Robert, E.

Inventor： THOMPSON, Bruce, M. ,  STENGEL, Robert, E.

IPC: H03F3/60

Abstract: A system and a method for providing an input to a distributed power amplifying system are provided. In an embodiment, a distributed power amplifying system includes a plurality of amplifying sections (102, 104, 106, and 108) and a plurality of drivers (110, 112, 114, and 116). Each of the plurality of drivers receives a common transmit signal (118) and an individual control signal (120, 122, 124, and 126). Each of the plurality of drivers independently preconditions the common transmit signal, to provide a transmit output signal (128, 130, 132, and 134) to each of the plurality of amplifying sections. The common transmit signal provided to each of the plurality of drivers is preconditioned, based on the individual control signal.

公开(公告)号：WO2006052416A3

公开(公告)日：2006-08-31

申请号：PCT/US2005037858

申请日：2005-10-21

Applicant: MOTOROLA INC ,  CAFARO NICHOLAS G ,  GRADISHAR THOMAS L ,  STENGEL ROBERT E

Inventor： CAFARO NICHOLAS G ,  GRADISHAR THOMAS L ,  STENGEL ROBERT E

IPC: H04L7/00

CPC classification number: H04L7/0083 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00286 ,  H03L7/0812 ,  H04L7/0337

Abstract: A DPC (300) includes: a frequency source (310) for generating a clock signal; a delay line (320) for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device (330) for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices (500, 510, 520) and a combining network. A method for use in a DPC includes: receiving (400) a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting (410) at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating (420) an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.

Abstract translation: DPC（300）包括：用于产生时钟信号的频率源（310）; 延迟线（320），用于接收时钟信号并在输出抽头产生相移时钟信号; 数字控制装置（330），用于产生控制信号; 以及用于生成包括顺序逻辑设备（500,510,520）和组合网络的输出信号的加窗选择电路。 一种在DPC中使用的方法包括：基于识别延迟线上的第一输出抽头的期望输出信号接收（400）控制信号; 基于所述控制信号，在所述延迟线上选择（410）至少两个输出抽头以接收至少两个不同的相移时钟信号; 以及基于所述控制信号和所接收的基本上是所需输出信号的相移时钟信号来产生（420）输出信号。

公开(公告)号：WO2006039099A1

公开(公告)日：2006-04-13

申请号：PCT/US2005/032667

申请日：2005-09-14

Applicant: MOTOROLA, INC. ,  GRADISHAR, Thomas, L. ,  STENGEL, Robert, E.

Inventor： GRADISHAR, Thomas, L. ,  STENGEL, Robert, E.

IPC: H03B21/00

CPC classification number: G06F1/025 ,  G06F2211/902

Abstract: A direct digital synthesizer (DDS) (300) that uses a system for reducing spurious emissions in a digital-to-time converter (DTC) (317). The DDS (300) includes one or more dither sources (307) and a random access memory (RAM) (305). The RAM (305) utilizes a look-up table for storing delay error values by using an output of the look-up table which is combined with the dither source (307) to compensate unequal unit delay values in the DTC (317).

Abstract translation: 一种直接数字合成器（DDS）（300），其使用用于减少数字 - 时间转换器（DTC）中的杂散发射的系统（317）。 DDS（300）包括一个或多个抖动源（307）和随机存取存储器（RAM）（305）。 RAM（305）通过使用与抖动源（307）组合的查找表的输出来利用查找表来存储延迟误差值，以补偿DTC（317）中的不相等的单位延迟值。

公开(公告)号：WO2004105229A1

公开(公告)日：2004-12-02

申请号：PCT/US2004/015469

申请日：2004-05-18

Applicant: MOTOROLA, INC., a corporation of the State of Delaware ,  TOMERLIN, Andrew ,  STENGEL, Robert, E.

Inventor： TOMERLIN, Andrew ,  STENGEL, Robert, E.

IPC: H03B19/00

CPC classification number: H03L7/087 ,  H03K3/84 ,  H03K5/00006 ,  H03K5/1504 ,  H03L7/0812 ,  H04B1/707 ,  H04B2201/70707

Abstract: A frequency extension circuit, consistent with certain embodiments of the present invention has a first delay line (108) having a plurality of taps. The delay line receives a reference clock at an input with a clock rate of FREF. A second delay line (104, 150) also receives the reference clock at an input. A logic circuit (130, 134, …, 138, 140) combines signals from the delay line taps of the first delay line (108) with signals from the delay line taps of the second and/or first delay line (104, 150, 108) to produce a collection of clock pulses having a combined clock rate of FREF*2N. At least one of the delay lines can be locked to the reference clock using a delay locked loop. The clock pulses can be logically combined with a seed register (204) contents to produce a recursive sequence or with data for convolutional encoding, or with pilot data for correlation in a CDMA transceiver.

Abstract translation: 与本发明的某些实施例一致的频率扩展电路具有具有多个抽头的第一延迟线（108）。 延迟线在时钟速率为FREF的输入处接收参考时钟。 第二延迟线（104,150）还在输入处接收参考时钟。 逻辑电路（130,134，...，138,140）组合来自第一延迟线（108）的延迟线抽头的信号与来自第二和/或第一延迟线（104）的延迟线抽头的信号， 以产生具有FREF * 2N的组合时钟速率的时钟脉冲的集合。 使用延迟锁定环路，至少一个延迟线可以锁定到参考时钟。 时钟脉冲可以与种子寄存器（204）内容逻辑地组合以产生递归序列或用于卷积编码的数据，或者与用于CDMA收发器中的相关的导频数据相结合。

公开(公告)号：WO2009018199A2

公开(公告)日：2009-02-05

申请号：PCT/US2008/071312

申请日：2008-07-28

Applicant: MOTOROLA, INC. ,  NAGARAJ, Geetha B. ,  CAFARO, Nicholas G. ,  HEKMANN, Ralf ,  STENGEL, Robert E. ,  MILLER, Scott

Inventor： NAGARAJ, Geetha B. ,  CAFARO, Nicholas G. ,  HEKMANN, Ralf ,  STENGEL, Robert E. ,  MILLER, Scott

IPC: H03D3/00

CPC classification number: H03B21/02 ,  H03L7/0814

Abstract: A method and system for managing Digital to Time Conversion (DTC) is provided. The method comprises receiving a first Radio Frequency (RF) signal and a second RF signal. The second RF signal is a phase-shifted first RF signal. The method further comprises converting the first RF signal to a first Intermediate Frequency (IF) signal and the second RF signal to a second IF signal. Further, a time delay between the first IF signal and the second IF signal is estimated based on a time difference measurement technique. The second RF signal is processed based on the estimated time delay to compensate for a delay error associated with the second RF signal.

Abstract translation: 提供了一种用于管理数字到时间转换（DTC）的方法和系统。 该方法包括接收第一射频（RF）信号和第二RF信号。 第二RF信号是相移的第一RF信号。 该方法还包括将第一RF信号转换为第一中频（IF）信号，将第二RF信号转换为第二IF信号。 此外，基于时差测量技术来估计第一IF信号和第二IF信号之间的时间延迟。 基于估计的时间延迟来处理第二RF信号以补偿与第二RF信号相关联的延迟误差。

公开(公告)号：WO2005109647A3

公开(公告)日：2008-09-12

申请号：PCT/US2005008549

申请日：2005-03-14

Applicant: MOTOROLA INC ,  WILHITE JEFFREY B ,  CHARASKA JOSEPH A ,  GABATO JR MANUEL P ,  GAILUS PAUL H ,  STENGEL ROBERT E

Inventor： WILHITE JEFFREY B ,  CHARASKA JOSEPH A ,  GABATO MANUEL P JR ,  GAILUS PAUL H ,  STENGEL ROBERT E

IPC: H03L7/06 ,  H03K5/00 ,  H03K5/13 ,  H03L7/081 ,  H03L7/16

CPC classification number: H03L7/16 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/0812

Abstract: A delay-locked loop 300 that includes: an adjustable frequency source (320) for generating a clock signal (322) having an adjustable frequency; an adjustment and tap selection controller (310) for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line (330) configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit (370) for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.

Abstract translation: 延迟锁定环路300，其包括：用于产生具有可调频率的时钟信号（322）的可调频率源（320） 调整和抽头选择控制器（310），用于根据第二频率确定第一频率，并使频率源将时钟信号的频率调整到基本上第一频率;第二频率是期望的频率 第一输出信号; 延迟线（330），被配置为接收用于产生多个相移时钟信号的时钟信号; 以及第一选择电路（370），用于接收多个相移时钟信号，并用于在调整和抽头选择控制器的控制下一次一个地选择第一个相移时钟信号序列，用于产生 第一输出信号具有基本上第二频率。

公开(公告)号：WO2007104010A2

公开(公告)日：2007-09-13

申请号：PCT/US2007/063565

申请日：2007-03-08

Applicant: MOTOROLA, INC. ,  CAFARO, Nicholas, G. ,  GRADISHAR, Thomas, L. ,  STENGEL, Robert, E.

Inventor： CAFARO, Nicholas, G. ,  GRADISHAR, Thomas, L. ,  STENGEL, Robert, E.

IPC: H03H11/26

CPC classification number: H03H11/265 ,  H03K5/131 ,  H03K2005/00065 ,  H03L7/1806

Abstract: Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.

Abstract translation: 改进在有限分辨率的延迟线中出现的量化误差。 包含数控振荡器（NCO）和数字 - 相位转换器（DPC）的直接数字合成器（DDS）放置在锁相环（PLL）的反馈环路中。 DDS用作压控振荡器（VCO）频率的分数分频器，使得DDS的参考频率变为可变。 然后可以调整由DDS延迟线提供的边缘的对准。 通过利用独立的可调谐延迟元件来减少DDS延迟线中的不匹配误差。

公开(公告)号：WO2005072298A2

公开(公告)日：2005-08-11

申请号：PCT/US2005/002138

申请日：2005-01-25

Applicant: MOTOROLA, INC. ,  TOMERLIN, Andrew, T. ,  STENGEL, Robert, E.

Inventor： TOMERLIN, Andrew, T. ,  STENGEL, Robert, E.

IPC: H03H11/26 ,  H03K5/00 ,  H03K5/13 ,  H03L7/08 ,  H03L7/081 ,  H03L7/16

CPC classification number: H03L7/0802 ,  H03K5/133 ,  H03K2005/00019 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/16

Abstract: A configurable circuit consistent with certain embodiments has a variable length delay line (10), the delay line (10) having an input (24) and having N delay elements (12, 14, 16, 18,…, 20) to provide a plurality of N delayed outputs (T(0) through T(N)). The variable length delay line (10) also has a number of active delay elements determined by a program command. A configurable processing array (32) receives the delayed outputs from the active delay elements and secondary data (38). The configurable processing array has an array of configurable circuit elements (104, 130, 150). The configurable processing array is configured to process the delayed outputs and the secondary data (38) in a manner for which the invention is to be used. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract translation: 与某些实施例一致的可配置电路具有可变长度延迟线（10），延迟线（10）具有输入（24）并且具有N个延迟元件（12,14,16,18，...，20） 提供多个N个延迟输出（T（0）至T（N））。 可变长度延迟线（10）还具有由程序命令确定的多个有效延迟元件。 可配置处理阵列（32）从主动延迟元件和辅助数据（38）接收延迟的输出。 可配置处理阵列具有可配置电路元件（104,130,150）的阵列。 可配置处理阵列被配置为以将要使用本发明的方式处理延迟的输出和辅助数据（38）。 该摘要不被认为是限制性的，因为其它实施例可能偏离本摘要中描述的特征。