公开(公告)号：KR1020130061997A

公开(公告)日：2013-06-12

申请号：KR1020110128366

申请日：2011-12-02

Applicant: 삼성전자주식회사

Inventor： 이재규 ,  강영민 ,  이현주

IPC: G11C8/10 ,  G11C8/08 ,  H01L27/105 ,  H01L21/8239

CPC classification number: G11C8/10 ,  G11C8/08 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659

Abstract: PURPOSE: A high density semiconductor memory device is provided to reduce an occupied size of a selected element by including switching elements with a unit size of 4F2 without decreasing the occupied size of an activation area and a gate area. CONSTITUTION: A cell array area includes a lower structure, an upper structure, word lines(WL), and an alternative structure. The alternative structure is arranged between the lower structures and the upper structures. A decoding circuit controls voltages applied to the word lines. The decoding circuit applies a first voltage(V1) to a pair of adjacent word lines and applies a second voltage(V2) to the other word lines corresponding to inputted one word line address information.

Abstract translation: 目的：提供一种高密度半导体存储器件，通过包括单位尺寸为4F2的开关元件来减少所选元件的占用尺寸，而不会减小激活区域和栅极区域的占用尺寸。 构成：单元阵列区域包括下部结构，上部结构，字线（WL）和替代结构。 替代结构布置在下部结构和上部结构之间。 解码电路控制施加到字线的电压。 解码电路对一对相邻字线施加第一电压（V1），并对与输入的一个字线地址信息对应的其他字线施加第二电压（V2）。

公开(公告)号：KR1020130037550A

公开(公告)日：2013-04-16

申请号：KR1020110102008

申请日：2011-10-06

Applicant: 삼성전자주식회사

Inventor： 강영민 ,  이상만 ,  김형우 ,  박기철

IPC: H01L27/04

CPC classification number: H01L23/585 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A semiconductor chip and a manufacturing method thereof are provided to form different semiconductor chips in one semiconductor chip. CONSTITUTION: A silicon layer is formed(S110). A first layer including a first sealing and a second sealing is formed in the upper part of the silicon layer(S120). The first sealing covers a first chip region. The second sealing covers a second chip region. Whether a necessary semiconductor chip is formed or not is determined(S131). A second layer connecting the first chip region to an external terminal is formed(S132). A second layer connecting the first chip region or the second chip region to the external terminal is formed(S133). [Reference numerals] (AA) Start; (BB) End; (S110) Forming a silicon layer; (S120) Forming a first layer including a first sealing and a second sealing; (S131) Manufactured chip is a first chip?; (S132) Forming a second layer connecting the first chip region to an external terminal; (S133) Forming a second layer connecting the first chip region or the second chip region to the external terminal;

Abstract translation: 目的：提供半导体芯片及其制造方法，以在一个半导体芯片中形成不同的半导体芯片。 构成：形成硅层（S110）。 在硅层的上部形成包括第一密封和第二密封的第一层（S120）。 第一密封件覆盖第一芯片区域。 第二密封件覆盖第二芯片区域。 确定是否形成必要的半导体芯片（S131）。 形成将第一芯片区域与外部端子连接的第二层（S132）。 形成将第一芯片区域或第二芯片区域连接到外部端子的第二层（S133）。 （附图标记）（AA）开始; （BB）结束; （S110）形成硅层; （S120）形成包括第一密封和第二密封的第一层; （S131）制造芯片是第一芯片？ （S132）形成将第一芯片区域连接到外部端子的第二层; （S133）形成将第一芯片区域或第二芯片区域连接到外部端子的第二层;

公开(公告)号：KR1020090090597A

公开(公告)日：2009-08-26

申请号：KR1020080015907

申请日：2008-02-21

Applicant: 삼성전자주식회사

Inventor： 이은선 ,  강영민

IPC: H01L27/105

CPC classification number: G11C11/22 ,  H01L27/11504

Abstract: A ferroelectric random access memory device and a method of manufacturing the same are provided to reduce parasitic capacitance generated in a unit cell since the number of word lines are small and the interval between conductive pattern is wide. In a ferroelectric random access memory device and a method of manufacturing the same, a first ferroelectrics capacitor(C1) is connected between the word line(W/L1-W/L4) and bit line(B/L). A second ferroelectrics capacitor(C2) is connected to word lines between the bit line bar. A first plate line(P/L1) is connected to the upper electrodes of first ferroelectrics capacitors, and a second plate line(P/L2) is connected to the upper electrode of second ferroelectrics capacitors.

Abstract translation: 提供了一种铁电随机存取存储器件及其制造方法，以减少单位单元中产生的寄生电容，因为字线数量小，并且导电图案之间的间隔较宽。 在铁电随机存取存储器件及其制造方法中，第一铁电电容器（C1）连接在字线（W / L1-W / L4）和位线（B / L）之间。 第二铁电电容器（C2）连接到位线条之间的字线。 第一板线（P / L1）连接到第一铁电电容器的上电极，第二板线（P / L2）连接到第二铁电体的上电极。