公开(公告)号：KR1020140052825A

公开(公告)日：2014-05-07

申请号：KR1020130105604

申请日：2013-09-03

Applicant: 삼성전자주식회사

Inventor： 윤용식 ,  차수호 ,  강동석 ,  김찬경

IPC: G11C13/00 ,  G11C7/06 ,  G11C11/15

CPC classification number: G11C13/0069 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1084 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0002 ,  G11C13/004 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

Abstract: The embodiment of the present invention includes a level movement write driver in a sense amplifier for a resistive type memory. The write driver includes a cross-couple latch, a first output unit, a second output unit, and an input unit. The first output unit includes one or more first driving transistors which drive a first current through the first output unit without passing through the cross-couple latch. The second output unit includes one or more second driving transistors which drive a second current through the second output unit without passing through the cross-couple latch. The current flows of the output unit are separated from a latch circuit. For example, the consumption of a die area is reduced by not including two PMOS transistors which are serially connected. According to the embodiment of the present invention, a single control signal for driving the write driver is used.

Abstract translation: 本发明的实施例包括用于电阻型存储器的读出放大器中的电平移动写入驱动器。 写驱动器包括交叉耦合锁存器，第一输出单元，第二输出单元和输入单元。 第一输出单元包括一个或多个第一驱动晶体管，其驱动通过第一输出单元的第一电流，而不通过交叉耦合锁存器。 第二输出单元包括一个或多个第二驱动晶体管，其驱动通过第二输出单元的第二电流，而不通过交叉耦合锁存器。 输出单元的电流与锁存电路分离。 例如，通过不包括串联连接的两个PMOS晶体管来减少管芯​​区域的消耗。 根据本发明的实施例，使用用于驱动写入驱动器的单个控制信号。

公开(公告)号：KR1020140004013A

公开(公告)日：2014-01-10

申请号：KR1020130074661

申请日：2013-06-27

Applicant: 삼성전자주식회사

Inventor： 윤용식 ,  차수호 ,  김찬경

IPC: G11C13/00 ,  G11C7/06

CPC classification number: G11C7/065 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0002 ,  G11C13/004 ,  G11C2013/0042

Abstract: Embodiments of the present invention include sense amplifiers of a resistive memory, each of the sense amplifiers including differential output terminals, first and second input terminals, a pre-charge section, and other components arranged so that current is reused during at least a "set" or "amplification" stage of the sense amplifier, thereby reducing overall current consumption of the circuit, and improving noise immunity. A voltage level of a high-impedance output terminal is changed in response to a delta average current between a reference line current and a bit line current. During a "go" or "latch" stage of operation, a logical value "0" or "1" is latched at the differential output terminals based on positive feedback of a latch circuit. Also, a current mirror circuit can be used in conjunction with the sense amplifier circuit, and the sense amplifier includes the capability of read/re-write operation.

Abstract translation: 本发明的实施例包括电阻式存储器的读出放大器，每个读出放大器包括差分输出端子，第一和第二输入端子，预充电部分和布置成使得电流在至少一个“集合” “或”放大“级，从而降低电路的总体电流消耗，并提高抗噪声能力。 响应于参考线电流和位线电流之间的增量平均电流，高阻抗输出端子的电压电平发生变化。 在“去”或“锁存”操作阶段期间，基于锁存电路的正反馈，在差分输出端子处锁存逻辑值“0”或“1”。 此外，电流镜电路可以与读出放大器电路结合使用，并且读出放大器包括读/写写操作的能力。

公开(公告)号：KR1020100082164A

公开(公告)日：2010-07-16

申请号：KR1020090001523

申请日：2009-01-08

Applicant: 삼성전자주식회사

Inventor： 김찬경

IPC: H03K3/023 ,  H03F3/45 ,  H03L7/099

CPC classification number: H03L7/099 ,  H03K3/0231 ,  H03L2207/06

Abstract: PURPOSE: An oscillator is provided to generate a multi phase clock using a complementation fully differential amplifier, thereby reducing power consumption. CONSTITUTION: The first complementation fully differential amplifier outputs the first output signal(OUT) which complementarily and differentially amplifies signals applied to the first input terminal and the second input terminal. The second complementation fully differential amplifier outputs the second output signal(OUTB) which has a completely different differential phase from the first output signal by completely and differentially amplifying signals applied to the third input terminal and the fourth input terminal. An output terminal of the first complementation fully differential amplifier is connected to the third and fourth input terminals of the second complementation fully differential amplifier. An output terminal of the second complementation fully differential amplifier is connected to the first and second input terminals of the first complementation fully differential amplifier. The first complementation fully differential amplifier and the second complementation fully differential amplifier have the same structure or the same amplifying performance.

Abstract translation: 目的：提供振荡器来产生使用互补全差分放大器的多相时钟，从而降低功耗。 构成：第一互补全差分放大器输出第一输出信号（OUT），其对施加到第一输入端和第二输入端的信号进行互补和差分放大。 第二互补全差分放大器通过完全和差分放大施加到第三输入端和第四输入端的信号，输出与第一输出信号完全不同的差分相位的第二输出信号（OUTB）。 第一互补全差分放大器的输出端连接到第二互补全差分放大器的第三和第四输入端。 第二互补全差分放大器的输出端连接到第一互补全差分放大器的第一和第二输入端。 第一互补全差分放大器和第二互补全差分放大器具有相同的结构或相同的放大性能。

公开(公告)号：KR100871701B1

公开(公告)日：2008-12-08

申请号：KR1020070016121

申请日：2007-02-15

Applicant: 삼성전자주식회사

Inventor： 김찬경

IPC: H04B3/02

CPC classification number: H04L25/0272

Abstract: 본 발명은 3개 전송 라인을 이용하여 3 비트 데이터를 차동 모드로 송수신하는 신호 전송 장치 및 방법에 대하여 개시된다. 신호 전송 장치는, 3개의 전송 라인들과, 제1 내지 제3 송신 데이터들을 암호화하여 다수개의 전압 레벨들로 출력되는 제1 내지 제3 전송 데이터들을 발생하고, 전송 라인들로 전송하는 신호 송신부, 그리고 제1 내지 제3 전송 데이터들을 수신하고, 제1 내지 제3 전송 데이터들 간의 중간 레벨을 모니터링하여 제1 내지 제3 수신 데이터로 복원하는 신호 수신부를 포함한다. 신호 전송 장치는, 3개의 전송 라인들을 이용하여 8가지 패턴의 3 비트 랜덤 데이터 통신이 가능하다.
3 비트 데이터 통신, 신호 전송 장치, 중간 레벨

公开(公告)号：KR100607196B1

公开(公告)日：2006-08-01

申请号：KR1020040052055

申请日：2004-07-05

Applicant: 삼성전자주식회사

Inventor： 김찬경

IPC: G11C29/00

CPC classification number: G11C29/12015 ,  G11C29/1201 ,  G11C29/14

Abstract: 본 발명은 반도체 메모리 장치 및 이 장치의 테스트 방법을 공개한다. 이 장치는 제1 클럭 신호에 응답하여 데이터를 입출력하는 메모리, 제2 클럭 신호에 응답하여 입력되는 데이터를 변환하여 출력하는 입력 변환 수단, 및 상기 제2 클럭 신호에 응답하여 제1 테스트 모드 시에는 상기 메모리로부터 출력되는 데이터를 변환하여 출력하고, 제2 테스트 모드 시에는 상기 입력 변환 수단으로부터 출력되는 데이터를 변환하여 출력하는 출력 변환 수단을 구비하는 것을 특징으로 한다. 따라서, 반도체 메모리 장치가 복수개의 주파수 영역을 가지는 경우, 복수개의 주파수 영역 중 어떤 영역에서 불량이 발생했는지를 파악할 수 있다.

Abstract translation: 本发明公开了一种半导体存储器件及其测试方法。 该设备包括：存储器，用于响应于第一时钟信号而输入和输出数据;输入转换装置，用于转换并输出响应于第二时钟信号而输入的数据; 以及输出转换装置，用于转换并输出从存储器输出的数据，并在第二测试模式下转换并输出从输入转换装置输出的数据。 因此，当半导体存储器件具有多个频率区域时，可以掌握多个频率区域中的哪一个发生缺陷。

公开(公告)号：KR1020060036721A

公开(公告)日：2006-05-02

申请号：KR1020040085802

申请日：2004-10-26

Applicant: 삼성전자주식회사

Inventor： 김찬경

IPC: G11C7/10

CPC classification number: H04L25/0272 ,  H03K21/10

Abstract: In an output driver circuit and method, a control circuit generates a control signal in response to a current internal data signal. An output driver generates an output data signal in response to the control signal. A pre-emphasis circuit adjusts a current flowing through a node having the control signal generated thereon in response to a previous internal data signal. The pre-emphasis circuit may also adjust the output signal in response to the previous internal data signal.

公开(公告)号：KR1020060012410A

公开(公告)日：2006-02-08

申请号：KR1020040061092

申请日：2004-08-03

Applicant: 삼성전자주식회사

Inventor： 김찬경

IPC: G11C11/40 ,  G11C11/4093

CPC classification number: G11C7/16 ,  G11C7/1048 ,  G11C7/22 ,  G11C11/4093

Abstract: A memory device for storage of digitally formatted data can include a Digital to Analog Converter (DAC) circuit that is configured to convert digitally formatted data received from outside the memory device to analog formatted data. An Analog to Digital Converter (ADC) circuit is coupled to the DAC circuit and is configured to convert the analog formatted data to the digitally formatted data for storage in the memory device. Related methods are also disclosed.

公开(公告)号：KR1020040041985A

公开(公告)日：2004-05-20

申请号：KR1020020070098

申请日：2002-11-12

Applicant: 삼성전자주식회사

Inventor： 최정환 ,  김찬경

IPC: H03L7/08

Abstract: PURPOSE: A delay locked loop(DLL) is provided to output the inner clock signal with positioning it at the center of the effective data by automatically controlling the phase of the inner clock signal in the DLL. CONSTITUTION: A delay locked loop(DLL) includes a first DLL, a phase difference detection and counting block(100) and a second DLL. The first DLL generates a first inner clock signal of which phase is synchronized to the external clock signal by using a signal generated by detecting and counting the phase difference of the external clock signal and the first inner clock signal. The phase difference detection and counting block(100) performs the counting by detecting the phase difference between the first inner clock signal and the second inner clock signal. And, the second DLL generates the second inner clock signal with correcting the phase of the first inner clock signal by using a signal which is obtained by adding a signal generated by performing the detection and counting the phase difference between the external clock signal and the first inner clock signal to a signal outputted from the phase difference detection and counting block(100).

Abstract translation: 目的：通过自动控制DLL内部时钟信号的相位，提供延迟锁定环（DLL）以输出内部时钟信号，将其定位在有效数据的中心。 构成：延迟锁定环（DLL）包括第一DLL，相位差检测和计数块（100）和第二DLL。 第一DLL通过使用通过检测和计数外部时钟信号和第一内部时钟信号的相位差产生的信号来产生其相位与外部时钟信号同步的第一内部时钟信号。 相位差检测和计数块（100）通过检测第一内部时钟信号和第二内部时钟信号之间的相位差来执行计数。 并且，第二DLL通过使用通过将通过执行检测生成的信号相加而获得的信号来校正第一内部时钟信号的相位，并且对外部时钟信号和第一内部时钟信号的第一 内部时钟信号输出到从相位差检测和计数块（100）输出的信号。

公开(公告)号：KR1020040039916A

公开(公告)日：2004-05-12

申请号：KR1020020068155

申请日：2002-11-05

Applicant: 삼성전자주식회사

Inventor： 김찬경

IPC: H03K5/13

CPC classification number: H03H11/26

Abstract: PURPOSE: A delayed tap signal generation circuit for controlling a delay difference by using interpolation of two input clocks is provided to control a delay difference between output tap signals by using the inputted offset. CONSTITUTION: A delayed tap signal generation circuit for controlling a delay difference by using interpolation of two input clocks includes a first tap signal generation circuit(210) and a second tap signal generation circuit(220). The first tap signal generation circuit(210) receives the first and the second clocks having a predetermined phase difference and generates the first tap signal corresponding to the offset in response to the first clock, the second clock, and the offset. The first tap signal is delayed as much as the first delay difference. The second tap signal generation circuit(220) receives the first and the second clocks and generates the second tap signal in response to the first clock, the second clock, and the offset. The first and the second tap signals are generated by interpolating the first and the second clocks in response to the offset.

Abstract translation: 目的：提供通过使用两个输入时钟的内插来控制延迟差的延迟抽头信号发生电路，以通过使用输入的偏移来控制输出抽头信号之间的延迟差。 构成：通过使用两个输入时钟的插值来控制延迟差的延迟抽头信号发生电路包括第一抽头信号产生电路（210）和第二抽头信号产生电路（220）。 第一抽头信号发生电路（210）接收具有预定相位差的第一和第二时钟，并且响应于第一时钟，第二时钟和偏移产生与偏移相对应的第一抽头信号。 第一抽头信号与第一延迟差一样延迟。 第二抽头信号发生电路（220）接收第一和第二时钟，并且响应于第一时钟，第二时钟和偏移产生第二抽头信号。 第一和第二抽头信号是通过响应于偏移量插入第一和第二时钟而产生的。

公开(公告)号：KR1020040027111A

公开(公告)日：2004-04-01

申请号：KR1020020058858

申请日：2002-09-27

Applicant: 삼성전자주식회사

Inventor： 김찬경

IPC: H03L7/095

Abstract: PURPOSE: A delayed locked loop(DLL) is provided to enable a user to know whether a misoperation of a semiconductor memory device is due to the delayed locked loop or not by detecting clock synchronization. CONSTITUTION: A delayed locked loop(DLL) provided with a circuit for detecting the synchronization status of a clock includes a phase detector(210), a phase mixer(220) and a clock synchronization detector. The phase detector(210) detects the difference between the external clock and the internal clock by receiving the internal and the output clocks and outputs the detection result. The phase mixer(220) receives the output signal of the phase detector(210), enable the internal clock to be synchronized with the external clock and outputs the synchronized internal clock. And, the clock synchronization detector detects whether the internal clock is synchronized with the external clock or not. The phase mixer(220) is provided with a counter(221), a digital-analog converter(222) and an interpolation circuit(223).

Abstract translation: 目的：提供延迟锁定环（DLL），以使用户能够通过检测时钟同步来知道半导体存储器件的误操作是否是由延迟的锁定环路引起的。 构成：提供有用于检测时钟的同步状态的电路的延迟锁定环（DLL）包括相位检测器（210），相位混合器（220）和时钟同步检测器。 相位检测器（210）通过接收内部和输出时钟来检测外部时钟和内部时钟之间的差异，并输出检测结果。 相位混合器（220）接收相位检测器（210）的输出信号，使内部时钟与外部时钟同步并输出同步的内部时钟。 而且，时钟同步检测器检测内部时钟是否与外部时钟同步。 相位混合器（220）设置有计数器（221），数模转换器（222）和内插电路（223）。