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公开(公告)号:KR1020070024803A
公开(公告)日:2007-03-08
申请号:KR1020050080322
申请日:2005-08-30
Applicant: 삼성전자주식회사
IPC: G11C13/02
CPC classification number: G11C13/0023 , G11C13/0038 , G11C13/004
Abstract: A phase change memory device is provided to prevent an error of a read operation, by increasing the amplitude of a read current applied to a phase change memory cell located in a memory bank distant from a read circuit. A number of memory blocks comprise a number of phase change memory cells, respectively. A read circuit(300_2) controls the amplitude of a read current applied to the phase change memory cell, in correspondence to a block selection signal designating each memory block. The read circuit includes a first read current supply circuit(310) supplying a first read current during a read operation, and a second read current supply circuit(320) supplying a second read current in response to the block selection signal during the read operation.
Abstract translation: 提供相变存储器件以通过增加施加到位于远离读取电路的存储体中的相变存储器单元的读取电流的幅度来防止读取操作的错误。 多个存储器块分别包括多个相变存储器单元。 读取电路(300_2)对应于指定每个存储器块的块选择信号来控制施加到相变存储单元的读取电流的幅度。 读取电路包括在读取操作期间提供第一读取电流的第一读取电流供应电路(310)和在读取操作期间响应于块选择信号提供第二读取电流的第二读取电流供应电路(320)。
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公开(公告)号:KR100674997B1
公开(公告)日:2007-01-29
申请号:KR1020050097269
申请日:2005-10-15
Applicant: 삼성전자주식회사
IPC: G11C13/02
Abstract: A phase-change random access memory device and a read operation control method using the same are provided to suppress the deterioration of a phase change material by preventing peak current applied to a phase change memory cell. A memory cell array(MCA) includes a plurality of phase change memory cells. A plurality of word lines(WL1~WLm) are connected to each phase change memory cell. The voltage level of the word line connected to the selected phase change memory cell includes two or more stages having different voltage levels, in a read operation. The voltage level of the word line includes two or more stages having a sequentially increasing voltage level.
Abstract translation: 提供了一种相变随机存取存储器件和使用该相变随机存取存储器件的读取操作控制方法,以通过防止施加到相变存储器单元的峰值电流来抑制相变材料的劣化。 存储器单元阵列(MCA)包括多个相变存储器单元。 多个字线(WL1〜WLm)连接到每个相变存储单元。 在读取操作中,连接到所选相变存储器单元的字线的电压电平包括具有不同电压电平的两个或更多个级。 字线的电压电平包括具有顺序增加的电压电平的两个或更多个级。
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