公开(公告)号：KR1020170064777A

公开(公告)日：2017-06-12

申请号：KR1020150170665

申请日：2015-12-02

Applicant: 삼성전자주식회사

Inventor： 이현의 ,  유혜승 ,  윤원주 ,  송인달

IPC: G11C7/10 ,  G11C7/04

CPC classification number: G11C7/12 ,  G06F3/0608 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0673 ,  G06F13/4086 ,  G11C7/02 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/56012 ,  G11C2029/5602 ,  G11C2207/105

Abstract: ZQ 핀없이캘리브레이션동작을수행하는메모리장치가개시된다. 메모리장치는데이터입출력패드의임피던스매칭을위하여, 데이터입출력패드를터미네이션시키는풀-업캘리브레이션코드와풀-다운캘리브레이션코드를발생하는캘리브레이션회로를포함한다. 캘리브레이션회로는사용되지않는패드에연결되는외부저항에기초하여제1 및제2 기준저항부들을트리밍하는 1차캘리브레이션동작과트리밍된제2 기준저항부에기초하여풀-업캘리브레이션코드와풀-다운캘리브레이션코드를발생하는 2차캘리브레이션동작을수행한다.

Abstract translation: 公开了一种用于在没有ZQ引脚的情况下执行校准操作的存储器件。 存储器件包括用于端接数据输入/输出焊盘的上拉校准码和用于产生用于数据输入/输出焊盘的阻抗匹配的下拉校准码的校准电路。 连接到基于第一mitje所述未用焊盘的外部电阻为基础的校准电路第二参考所述第二参考和所述经修整的第一校准操作来修整电阻单元电阻部拉校准码和下拉校准 并执行二次校准操作以生成代码。

公开(公告)号：KR1020140109214A

公开(公告)日：2014-09-15

申请号：KR1020130061057

申请日：2013-05-29

Applicant: 삼성전자주식회사

Inventor： 심용 ,  송인달

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/10 ,  G11C11/4076

CPC classification number: G11C7/22 ,  G11C7/1063 ,  G11C7/109 ,  G11C11/4076 ,  G11C2207/2272

Abstract: A semiconductor memory device and a method for operating the same are provided. The semiconductor memory device comprises: a buffer for outputting a first delay signal by receiving a first signal; a command decoder for outputting a second signal; a mask pulse signal generator for generating a mask pulse signal by receiving the first delay signal and the second signal; and a signal reshaper for reshaping the first delay signal or the second signal by receiving the first delay signal, the second signal, and the mask pulse signal.

Abstract translation: 提供半导体存储器件及其操作方法。 半导体存储器件包括：缓冲器，用于通过接收第一信号来输出第一延迟信号; 用于输出第二信号的命令解码器; 掩模脉冲信号发生器，用于通过接收第一延迟信号和第二信号来产生掩模脉冲信号; 以及用于通过接收第一延迟信号，第二信号和掩模脉冲信号来重新形成第一延迟信号或第二信号的信号整形器。

公开(公告)号：KR1020130031650A

公开(公告)日：2013-03-29

申请号：KR1020110095354

申请日：2011-09-21

Applicant: 삼성전자주식회사

Inventor： 송인달 ,  최정환 ,  양윤석

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1057 ,  G11C7/1084 ,  H03K19/0005 ,  G11C7/10 ,  G11C7/22

Abstract: PURPOSE: A method and apparatus for operating a memory device are provided to issue a command according to the level of a control signal inputted through a control pin. CONSTITUTION: ODT signals(ODT0,ODT2,ODT3,ODT3) are received through an ODT pin. A command is issued or an ODT circuit is controlled. The resistance of the final resistor in the ODT circuit is changed or the ODT circuit is turned on or off. The command is issued in response to the ODT signal when the level of the ODT signal is toggled at each edge of a clock signal.

Abstract translation: 目的：提供一种用于操作存储器件的方法和装置，以根据通过控制引脚输入的控制信号的电平发出命令。 构成：通过ODT引脚接收ODT信号（ODT0，ODT2，ODT3，ODT3）。 发出命令或控制ODT电路。 ODT电路中的最终电阻的电阻发生变化，或者ODT电路导通或关断。 当在时钟信号的每个边缘切换ODT信号的电平时，响应于ODT信号发出该命令。

公开(公告)号：KR1020080011918A

公开(公告)日：2008-02-11

申请号：KR1020060072659

申请日：2006-08-01

Applicant: 삼성전자주식회사

Inventor： 송인달

IPC: H03L7/085 ,  H03L7/081

CPC classification number: H03L7/0814 ,  H03L7/0818

Abstract: A delay locked loop circuit and a jitter reducing method thereof are provided to decrease an amount of bang-bang jitters in the DLL(Delay Locked Loop) by mixing two delay signals around a middle point between first edges of the delay signals. An auxiliary phase shifter(31) receives a clock signal and outputs a clock signal with or without a delay. A coarse delay line(32) receives an output signal from the auxiliary phase shifter, sequentially delays the received signal, and outputs plural delay signals. A phase selector(33) selects two of the delay signals and outputs the selected signals. A phase mixer(34) phase-mixes the two delays signals and outputs a feedback signal. A phase detector(35) compares the clock signal with the feedback signal and generates a detection signal corresponding to a phase difference between the clock signal and the feedback signal. A control circuit(36) controls the auxiliary phase shifter, the phase selector, and the phase mixer in response to the detection signal.

Abstract translation: 提供了一种延迟锁定环路电路及其抖动降低方法，通过在延迟信号的第一个边缘之间的中点附近混合两个延迟信号来减小DLL（延迟锁定环路）中的轰击抖动的量。 辅助移相器（31）接收时钟信号并输出​​具有或不具有延迟的时钟信号。 粗延迟线（32）接收来自辅助移相器的输出信号，顺序地延迟接收信号，并输出多个延迟信号。 相位选择器（33）选择两个延迟信号并输出​​所选择的信号。 相位混合器（34）对两个延迟信号进行相位混合并输出反馈信号。 相位检测器（35）将时钟信号与反馈信号进行比较，并产生对应于时钟信号和反馈信号之间的相位差的检测信号。 控制电路（36）响应于检测信号控制辅助移相器，相位选择器和相位混频器。

公开(公告)号：KR100743493B1

公开(公告)日：2007-07-30

申请号：KR1020060016499

申请日：2006-02-21

Applicant: 삼성전자주식회사

Inventor： 송인달

IPC: H03L7/081

Abstract: An adaptive delay locked loop is provided to increase a fixed time and reduce a bang-bang jitter by updating a phase of an output clock signal to a frequency and a phase difference smaller than a loop bandwidth during a locking state. An adaptive delay locked loop includes an input buffer(11), a duty/cycle corrector and multiplexer(12), a delay line(13), a control logic(14), a local clock generator(15), a clock driver(16), a replica path(17), and a phase detector(18). The delay line(13) generates an output clock signal having a predetermined phase delay. The clock driver(16) receives and amplifies the output clock signal. The replica path delays the output clock signal from the delay line(13). The phase detector(18) detects a phase difference between the input clock signal and the delayed output clock signal from the replica path and generates a phase detection signal based on the phase difference signal. The control logic(14) outputs a phase control signal according to the phase difference between the input clock signal and the delayed output clock signal.

Abstract translation: 提供自适应延迟锁定环以通过在锁定状态期间将输出时钟信号的相位更新为小于环路带宽的频率和相位差来增加固定时间并减少砰砰声抖动。 自适应延迟锁定环包括输入缓冲器（11），占空比/周期校正器和多路复用器（12），延迟线（13），控制逻辑（14），本地时钟发生器（15），时钟驱动器 16），复制路径（17）和相位检测器（18）。 延迟线（13）产生具有预定相位延迟的输出时钟信号。 时钟驱动器（16）接收并放大输出时钟信号。 复制路径延迟来自延迟线（13）的输出时钟信号。 相位检测器（18）从复制路径检测输入时钟信号和延迟输出时钟信号之间的相位差，并基于相位差信号生成相位检测信号。 控制逻辑（14）根据输入时钟信号和延迟的输出时钟信号之间的相位差输出相位控制信号。