감지증폭기의 센싱속도를 향상시킬 수 있는 반도체메모리장치의 감지증폭기 구동회로
    22.
    发明公开
    감지증폭기의 센싱속도를 향상시킬 수 있는 반도체메모리장치의 감지증폭기 구동회로 失效
    用于提高感测放大器感应速度的半导体存储器件的感测放大器驱动电路

    公开(公告)号:KR1020030060513A

    公开(公告)日:2003-07-16

    申请号:KR1020020001246

    申请日:2002-01-09

    Inventor: 송태중 임은경

    CPC classification number: G11C7/06 G11C11/419 G11C2207/065

    Abstract: PURPOSE: A sense amplifier drive circuit of a semiconductor memory device for improving a sensing speed of a sense amplifier is provided to improve the performance of an SRAM by increasing the sensing speed. CONSTITUTION: A sense amplifier drive circuit is used for sensing and amplifying data of bit line couples connected to a bit cell. The sense amplifier drive circuit includes a plurality of delay inverters(81,83,85,87). The delay inverters are serially connected to each other. One of the delay inverters includes a plurality of NMOS transistors. The NMOS transistors are serially connected to an output terminal of the sense amplifier drive circuit. In addition, the NMOS transistors have gates connected to an input terminal of the sense amplifier. A beta ratio of the NMOS transistors is equal to a beta ratio of a pass transistor of the bit cell. The length of the NMOS transistors is equal to the length of the pass transistor of the bit cell.

    Abstract translation: 目的:提供用于提高读出放大器的感测速度的半导体存储器件的读出放大器驱动电路,通过增加感测速度来提高SRAM的性能。 构成:读出放大器驱动电路用于感测和放大连接到位单元的位线耦合的数据。 读出放大器驱动电路包括多个延迟反相器(81,83,85,87)。 延迟逆变器彼此串联连接。 一个延迟逆变器包括多个NMOS晶体管。 NMOS晶体管串联连接到读出放大器驱动电路的输出端。 此外,NMOS晶体管具有连接到读出放大器的输入端的栅极。 NMOS晶体管的β比率等于位单元的通过晶体管的β比。 NMOS晶体管的长度等于位单元的通过晶体管的长度。

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