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公开(公告)号：KR1020090106887A
公开(公告)日：2009-10-12
申请号：KR1020080032281
申请日：2008-04-07
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1675 , H01L45/1683 , G11C13/0004 , H01L21/28052
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to obtain high electric reliability by maintaining the resistance of a resistance memory element. CONSTITUTION: A semiconductor device includes an insulation layer(120), a reaction prevention layer(130), a lower electrode(145), a resistance memory element(155), and a top electrode(165). The insulation layer and the reaction prevention layer are successively stacked on a substrate(110). The bottom electrode has a lateral side surrounded with the reaction prevention layer and the insulation layer. The resistance memory element includes the metal oxide. The resistance memory element has the wider lower surface than the upper surface of the bottom electrode. The resistance memory element is positioned on the bottom electrode and the reaction prevention layer. The top electrode is formed on the resistance memory element. The reaction prevention layer prevents the resistance memory element from reacting with the silicon.
Abstract translation: 目的：提供半导体器件及其制造方法，以通过维持电阻存储元件的电阻来获得高电可靠性。 构成：半导体器件包括绝缘层（120），反应防止层（130），下电极（145），电阻存储元件（155）和顶电极（165）。 绝缘层和防反应层依次层叠在基板（110）上。 底部电极具有被反应防止层和绝缘层包围的侧面。 电阻记忆元件包括金属氧化物。 电阻记忆元件具有比底部电极的上表面更宽的下表面。 电阻记忆元件位于底部电极和反应防止层上。 顶电极形成在电阻存储元件上。 反应防止层防止电阻记忆元件与硅反应。
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公开(公告)号：KR1020090090563A
公开(公告)日：2009-08-26
申请号：KR1020080015848
申请日：2008-02-21
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247 , H01L21/336
CPC classification number: G11C13/02 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/31 , G11C2213/32 , H01L27/101 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/146 , H01L45/147 , H01L29/517
Abstract: Semiconductor devices having a resistive memory element is provided to obtain excellent heat reliability the reliability by forming a resistance memory element as a multi-level. A resistance memory element(130) is arranged on a substrate(100), and it has a multi-level resistance state through generation of disappearance of a platinum bridge(150). A first electrode(120) is connected to a first side of the resistance memory element, and a second electrode(140) is connected to the second side of the resistance memory element. The first step and the second end of the platinum bridge are contacted with the first electrode and the second electrode.
Abstract translation: 提供了具有电阻式存储元件的半导体器件，通过形成作为多电平的电阻存储元件来获得良好的可靠性的可靠性。 电阻存储元件（130）设置在基板（100）上，并且通过产生铂桥（150）的消失而具有多电平电阻状态。 第一电极（120）连接到电阻存储元件的第一侧，第二电极（140）连接到电阻存储元件的第二侧。 铂桥的第一步和第二端与第一电极和第二电极接触。
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公开(公告)号：KR100481175B1
公开(公告)日：2005-04-07
申请号：KR1020020046919
申请日：2002-08-08
Applicant: 삼성전자주식회사
IPC: G11C29/00
CPC classification number: G11C17/165 , G11C17/18 , G11C29/027 , G11C29/848
Abstract: 본 발명은 결함 메모리 로우를 스패어 메모리 로우로 교체하는 데 사용된 시프트 리던던시 회로들을 가지는 반도체 메모리 장치에 관한 것으로서, 2 개의 버퍼체인을 가지는 시프트 리던던시 회로와 시프트 리던던시 회로에 연결된 2 개의 퓨즈 및 2 개의 퓨즈절단 검출회로를 복수 개 구비하고 2 개의 스패어 메모리 로우를 각각 제어하기 위한 2 개의 스패어 셀 제어회로를 구비함으로써, 상하 양방향으로 메모리 로우의 시프트가 가능하고 하나의 메모리 셀 어레이 블록 내에 2 개의 결함 메모리 로우가 존재하는 경우에도 결함 메모리 로우를 스패어 메모리 로우로 교체가 가능한 것을 특징으로 한다.
본 발명에 따른 반도체 메모리 장치에 의하면 한 블록 내에 2 개의 결함 메모리 로우가 존재하는 경우에도 결함 메모리 로우를 스패어 메모리 로우로 교체가 가능하다. 또한, 본 발명에 따른 반도체 메모리 장치에 의하면 퓨즈 저항에 의한 누설전류가 감소하고 반도체 메모리 장치의 오동작을 방지할 수 있다.-
公开(公告)号：KR1020100093354A
公开(公告)日：2010-08-25
申请号：KR1020090012502
申请日：2009-02-16
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/04 , G11C13/0004 , H01L29/513 , H01L29/517 , H01L45/1233
Abstract: PURPOSE: A method for manufacturing a resistance memory device is provided to form a resistance oxide layer which is physically and chemically stabilized without an etching process by forming the resistance oxide layer through the diffusion of oxygen to the upper surface of the first electrode through a second electrode. CONSTITUTION: A first electrode(12) is formed inside a lower insulation layer(10). A second electrode(14) is formed on a first electrode. The second electrode is formed on the deposition process using an organic metal precursor. The upper surface of the first electrode connected to the second electrode is converted into a resistance oxidation layer(16) by diffusing the oxygen to the upper surface of the first electrode through the second electrode.
Abstract translation: 目的：提供一种用于制造电阻存储器件的方法，以形成物理和化学稳定的电阻氧化层，无需蚀刻工艺，通过通过第二电极通过氧气扩散到第一电极的上表面形成电阻氧化物层 电极。 构成：第一电极（12）形成在下绝缘层（10）的内部。 在第一电极上形成第二电极（14）。 使用有机金属前体在沉积工艺上形成第二电极。 通过第二电极将氧扩散到第一电极的上表面，将连接到第二电极的第一电极的上表面转换成电阻氧化层（16）。
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公开(公告)号：KR1020100007200A
公开(公告)日：2010-01-22
申请号：KR1020080067718
申请日：2008-07-11
Applicant: 삼성전자주식회사
CPC classification number: H01L21/76838 , B82Y40/00 , H01L21/32139 , H01L21/76837
Abstract: PURPOSE: A method for forming a semiconductor device is provided to implement high integration by reducing the width of components with a nano scale. CONSTITUTION: A nano structure is formed from a catalyst pattern. The nanostructure is grown on the catalyst pattern. An insulation layer(21) is formed on a substrate(10). The insulation layer surrounds the nano structure. The top of the nano structure is exposed by the planarization of the insulation layer. The opening is formed by removing the nano structure and the catalyst pattern. The opening is defined by the insulation layer. A variable resistance pattern(27) is formed in the opening.
Abstract translation: 目的：提供一种用于形成半导体器件的方法，通过减小纳米级元件的宽度来实现高集成度。 构成：由催化剂图案形成纳米结构。 纳米结构在催化剂图案上生长。 绝缘层（21）形成在基板（10）上。 绝缘层围绕纳米结构。 纳米结构的顶部通过绝缘层的平坦化暴露。 通过除去纳米结构和催化剂图案形成开口。 开口由绝缘层限定。 在开口中形成可变电阻图案（27）。
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Patent Agency Ranking6.发明授权다수 저항 상태를 갖는 저항 메모리 요소, 저항 메모리 셀및 그 동작 방법 그리고 상기 저항 메모리 요소를 적용한데이터 처리 시스템 有权다수저항상태를갖는저항메모리요소，저항메모리셀및그동작방법그리고상기저항메모리요소를를용한데이터처리시스템
公开(公告)号：KR100684908B1
公开(公告)日：2007-02-22
申请号：KR1020060002300
申请日：2006-01-09
Applicant: 삼성전자주식회사
IPC: G11C11/15
Abstract: A resistive memory element having multi-resistive states, a resistive memory cell and an operation method thereof, and a data processing system using the resistive memory element are provided to simplify a driving circuit of a memory device and to reduce a driving voltage, by making driving signals, such as a reset voltage, a set current and a read voltage, have the same polarity. In a resistive memory element indicating resistive states of numerous levels, the resistive memory element includes two-component metal oxide. The two-component metal oxide is changed to at least one middle resistive state having lower resistance than a high resistive state and a low resistive state having lower resistance than the middle resistive state, from the high resistive state, by applying a current.
Abstract translation: 通过制造具有多电阻状态的电阻存储元件，电阻式存储单元及其操作方法，以及使用该电阻式存储元件的数据处理系统，以简化存储器件的驱动电路并降低驱动电压 诸如复位电压，设定电流和读取电压之类的驱动信号具有相同的极性。 在指示多个电平的电阻状态的电阻存储元件中，电阻存储元件包括双组分金属氧化物。 通过施加电流，双组分金属氧化物从高电阻状态变为具有比高电阻状态低的电阻的至少一个中间电阻状态和具有比中间电阻状态低的电阻的低电阻状态。
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公开(公告)号：KR1020040013832A
公开(公告)日：2004-02-14
申请号：KR1020020046919
申请日：2002-08-08
Applicant: 삼성전자주식회사
IPC: G11C29/00
CPC classification number: G11C17/165 , G11C17/18 , G11C29/027 , G11C29/848
Abstract: PURPOSE: A semiconductor memory device having shift redundancy circuits is provided, which enables to replace a defective memory row with a spare memory row when there are two defective memory rows in one block. CONSTITUTION: The semiconductor memory device comprises a shift redundancy circuit having two buffer chains, and two fuses(FAU,FAD) connected to the shift redundancy circuit and a plurality of two fuse blowing detection circuits(FCU,FCD). And two spare cell control circuits(SPC1,SPC2) are for controlling two spare memory rows respectively. A shift in both direction of upward and downward is enabled, and a defective memory row can be replaced with a spare memory row when there are two defective memory rows in one memory cell array block.
Abstract translation: 目的：提供一种具有移位冗余电路的半导体存储器件，当在一个块中存在两个有缺陷的存储器行时，能够用备用存储器行替换有缺陷的存储器行。 构成：半导体存储器件包括具有两个缓冲链的移位冗余电路和连接到移位冗余电路的两个熔丝（FAU，FAD）和多个两个熔丝熔断检测电路（FCU，FCD）。 并且两个备用单元控制电路（SPC1，SPC2）分别用于控制两个备用存储器行。 在两个存储单元阵列块中存在两个缺陷存储器行时，允许向上和向下两个方向的移位，并且可以用备用存储器行替换有缺陷的存储器行。
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公开(公告)号：KR101526926B1
公开(公告)日：2015-06-10
申请号：KR1020080136239
申请日：2008-12-30
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: G11C13/0007 , G11C11/5685 , G11C13/0069 , G11C2013/0071 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/55 , G11C2213/77 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1608
Abstract: 저항메모리소자및 그제조방법에서, 상기저항메모리소자는제1 전극을포함한다. 상기제1 전극의상부면과접하고, 전계에의해저항이변화되는제1 금속산화막및 상기제1 금속산화막과다른물질로이루어지고, 상기제1 금속막보다얇은두께의제2 금속산화막이서로반복적층된저항산화구조물을포함한다. 또한, 상기저항산화구조물상에는제2 전극을포함한다. 상기저항메모리소자는리셋전류가감소되어고속동작이가능하고, 멀티레벨스위칭특성을가지므로데이터저장용량이증가된다.
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公开(公告)号：KR1020100078088A
公开(公告)日：2010-07-08
申请号：KR1020080136239
申请日：2008-12-30
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: G11C13/0007 , G11C11/5685 , G11C13/0069 , G11C2013/0071 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/55 , G11C2213/77 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/147
Abstract: PURPOSE: A resist ram and a method of manufacturing the same are provided to implement low power consumption and high switching speed by reducing a reset current. CONSTITUTION: A resistance memory device comprises a first electrode(100), a resistance oxidation structure(110), and a second electrode(114). The resistance oxidation structure is formed by laminating first metal oxide layer(106a-106f) and second metal oxide layer(108a-108e). The first metal oxide layer and the second metal oxide layer are comprised of different materials. The thickness of the second metal oxide layer is smaller than that of the first metal oxide layer. The second metal oxide layer is comprised of a metal rich-metal oxide. The second electrode is formed on the resistance oxidation structure water.
Abstract translation: 目的：提供抗蚀剂压头及其制造方法，通过减少复位电流来实现低功耗和高开关速度。 构成：电阻存储器件包括第一电极（100），电阻氧化结构（110）和第二电极（114）。 电阻氧化结构通过层叠第一金属氧化物层（106a-106f）和第二金属氧化物层（108a-108e）而形成。 第一金属氧化物层和第二金属氧化物层由不同的材料组成。 第二金属氧化物层的厚度小于第一金属氧化物层的厚度。 第二金属氧化物层由金属富金属氧化物构成。 第二电极形成在电阻氧化结构水上。
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公开(公告)号：KR1020090098189A
公开(公告)日：2009-09-17
申请号：KR1020080023416
申请日：2008-03-13
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: G11C13/0007 , G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/003 , G11C2213/31 , G11C2213/32 , G11C2213/78 , G11C2213/79 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1226 , H01L45/146 , H01L45/1633 , H01L27/0688
Abstract: A non-volatile memory device, a method of fabricating the same, and a processing system comprising the same are provided to reduce the material cost of the variable resistance. The inner electrode(500) is extended perpendicularity and is formed in the one side of the substrate(100). The first and the second outer electrode(410_1,420_2) intersecting with each inner electrode are arranged in both sides of the each inner electrode. The first and second outer electrodes are formed with multi-layer according to the extension direction of inner electrodes. The selection elements select the variable resistance(600). First outer portion electrodes are electrically connected with each other. The inner electrodes are connected to two per the active region.
Abstract translation: 提供非易失性存储器件，其制造方法和包括该非易失性存储器件的处理系统以减少可变电阻的材料成本。 内部电极（500）垂直延伸并形成在基板（100）的一侧。 与每个内部电极相交的第一和第二外部电极（410_1,420_2）布置在每个内部电极的两侧。 第一外电极和第二外电极根据内电极的延伸方向形成多层。 选择元件选择可变电阻（600）。 第一外部电极彼此电连接。 每个有源区域内部电极连接到两个电极。
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