公开(公告)号：KR1020070028926A

公开(公告)日：2007-03-13

申请号：KR1020050083712

申请日：2005-09-08

Applicant: 삼성전자주식회사

Inventor： 전상윤 ,  정성재 ,  이흥배 ,  이동현

IPC: H01F21/02

CPC classification number: H01F21/12 ,  H01F17/0013 ,  H01F2017/0046 ,  H01F2021/125

Abstract: A variable inductor is provided to maximize a change ratio of an inductance of the variable inductor by selectively applying a couple of differential signals to a second wiring unit and varying the inductance. A variable inductor includes a first wiring unit(110), a second wiring unit(120), and a switching unit(130). The first wiring unit(110) has both ends which receive a predetermined couple of differential signals. The second wiring unit(120) has both ends which receive a predetermined couple of differential signals. The switching unit(130) is switched on or off according to a predetermined control signal. The switching unit(130) applies the couple of differential signals to the second wiring unit(120) selectively. A direction of a magnetic flux which is generated by a current flowing on the first wiring unit(110) and a direction of a magnetic flux which is generated by a current flowing on the second wiring unit(120) are offset by the couple of differential signals.

Abstract translation: 提供可变电感器以通过选择性地将一对差分信号施加到第二布线单元并改变电感来最大化可变电感器的电感的变化率。 可变电感器包括第一布线单元（110），第二布线单元（120）和开关单元（130）。 第一接线单元（110）具有接收预定的一对差分信号的两端。 第二接线单元（120）具有接收预定的一对差分信号的两端。 切换单元（130）根据预定的控制信号被接通或断开。 切换单元（130）选择性地将一对差分信号施加到第二配线单元（120）。 由流过第一配线单元（110）的电流产生的磁通方向和由流过第二配线单元（120）的电流产生的磁通方向产生的磁通的方向被差动对 信号。

公开(公告)号：KR100652965B1

公开(公告)日：2006-12-01

申请号：KR1020050092373

申请日：2005-09-30

Applicant: 삼성전자주식회사

Inventor： 남일구 ,  어윤성 ,  정성재 ,  이흥배 ,  이귀로

IPC: H04B1/10

Abstract: A transmitter realized by a vertical BJT(Bipolar Junction Transistor) is provided to use a vertical BJT for at least a portion of circuit elements, thereby improving matching characteristics among the elements and solving DC(Direct Current) offset problems. A DAC(Digital to Analog Converter)(10) converts an inputted digital signal into an analog signal. A baseband analog filter(20) filters a particular band of a signal passing through the DAC(10). A phase conversion element(60) is applied with an LO(Local Oscillator) signal to output an in-phase LO signal and a quadrature LO signal. The first and second mixers mix the signal outputted from the filter(20) with the outputted in-phase and quadrature LO signals to individually output in-phase RF(Radio Frequency) and quadrature RF vector signals. A drive amplifier(40) amplifies the outputted RF signals. A switching element that comprises at least one of the DAC(10), the filter(20), the first and second mixers, and the drive amplifier(40) is realized as a vertical BJT.

Abstract translation: 提供由垂直BJT（双极结晶体管）实现的发射器，以对至少一部分电路元件使用垂直BJT，从而改善元件之间的匹配特性并解决DC（直流）偏移问题。 DAC（数模转换器）（10）将输入的数字信号转换为模拟信号。 基带模拟滤波器（20）对通过DAC（10）的信号的特定频带进行滤波。 相位转换元件（60）被施加LO（本地振荡器）信号以输出同相LO信号和正交LO信号。 第一和第二混频器将从滤波器（20）输出的信号与输出的同相和正交LO信号混合，以分别输出同相RF（射频）和正交RF矢量信号​​。 驱动放大器（40）放大输出的RF信号。 包括DAC（10），滤波器（20），第一和第二混频器以及驱动放大器（40）中的至少一个的开关元件被实现为垂直BJT。

公开(公告)号：KR100528347B1

公开(公告)日：2005-11-15

申请号：KR1020030068610

申请日：2003-10-02

Applicant: 삼성전자주식회사

Inventor： 정성재 ,  김훈태 ,  어윤성 ,  이광두 ,  전상윤

IPC: H03F1/22

CPC classification number: H03F1/223 ,  H01L27/0207 ,  H01L27/0705

Abstract: 이중 게이트 트랜지스터에 의한 캐스코드 앰프에 관해 개시한다. 앰프는 하나의 제1채널과, 상기 제1채널을 공유하는 제1, 제2게이트를 각각 가지는 제1트랜지스터 및 제2트랜지스터를 구비하며, 제1트랜지스터 및 제2트랜지스터 중의 어느 하나는 별도의 제2채널, 제2채널에 대응하는 게이트 및 제2채널에 인접하는 제 2 드레인 또는 제 2 소스를 가지는 제3트랜지스터와 병렬 접속되며, 상기 제3트랜지스터와 상기 제3트랜지스터와 병렬 접속되는 제1트랜지스터 또는 제2트랜지스터가 하나의 소스 또는 드레인을 공유하며, 상기 제3트랜지스터는 공유되지 않는 드레인 또는 소스를 갖춘다.
본 발명에 따르면 캐스코드 앰프를 이루는 두 트랜지스터의 게이트 폭을 차등화할 수 있고, 따라서 이중 게이트 트랜지스터의 구조적 한계에 따른 응용 제안을 크게 감소시킬 수 있다.

公开(公告)号：KR1020050032688A

公开(公告)日：2005-04-08

申请号：KR1020030068610

申请日：2003-10-02

Applicant: 삼성전자주식회사

Inventor： 정성재 ,  김훈태 ,  어윤성 ,  이광두 ,  전상윤

IPC: H03F1/22

CPC classification number: H03F1/223 ,  H01L27/0207 ,  H01L27/0705

Abstract: A dual gate cascade amplifier is provided to reduce the noise generated by the substrate resistance in RF CMOS circuit. A dual gate cascade amplifier includes a common source transistor and a common gate transistor. The common gate transistor is provided with a pair of parallel transistors. The pair of the parallel transistors have a pair of individual gates(G2a,G2b) and commonly owns the drain(D2). The sources of the parallel transistors are connected to the conductive lines(10) to maintain the equipotential. The conductive line(10) is prepared between the gate(G1) of the common source transistor and the gate(G2a) of the first parallel transistor of the common gate transistor, and also the conductive line is prepared on the end portion of the channel of the second parallel transistor.

Abstract translation: 提供双栅极级联放大器以减少由RF CMOS电路中的衬底电阻产生的噪声。 双栅级联放大器包括公共源极晶体管和公共栅极晶体管。 公共栅极晶体管设置有一对并联晶体管。 该对并联晶体管具有一对单独的栅极（G2a，G2b）并且共同拥有漏极（D2）。 并联晶体管的源极连接到导线（10）以保持等电位。 在公共源晶体管的栅极（G1）和公共栅极晶体管的第一并联晶体管的栅极（G2a）之间制备导线（10），并且在沟道的端部准备导线 的第二并联晶体管。