公开(公告)号：KR101345385B1

公开(公告)日：2013-12-24

申请号：KR1020070133606

申请日：2007-12-18

Applicant: 삼성전자주식회사

Inventor： 최재만 ,  권문석 ,  황승식 ,  김한수 ,  박진환

IPC: H01B1/20

CPC classification number: C09D11/322 ,  C09D11/52 ,  H01L51/0022

Abstract: 상기잉크젯인쇄용전극조성물은잉크젯인쇄시노즐에서의토출성능을개선하기위하여적절한점도를갖는바인더를채택함으로써, 노즐막힘없이잉크젯인쇄방식을사용하여집전체상에원하는패턴을얇고균일하고평탄하게제조하면서도경제적으로전극및 이차전지를형성할수 있게된다.

公开(公告)号：KR1020130128273A

公开(公告)日：2013-11-26

申请号：KR1020120052204

申请日：2012-05-16

Applicant: 삼성전자주식회사 ,  한양대학교 산학협력단

Inventor： 윤선미 ,  최재영 ,  김한수 ,  박호범 ,  권문석

IPC: H01M4/13 ,  H01M4/62 ,  H01M4/38 ,  H01M4/583

CPC classification number: H01M4/583 ,  H01M4/0404 ,  H01M4/0428 ,  H01M4/133 ,  H01M4/134 ,  H01M4/366 ,  H01M4/382 ,  H01M4/405 ,  H01M4/587 ,  H01M4/661 ,  H01M10/052 ,  H01M2004/027 ,  Y02E60/122 ,  Y02T10/7011

Abstract: The present invention relates to a negative electrode for a lithium battery which comprises a metallic layer containing lithium and a carbon material layer in a plate structure formed on the surface of the metallic layer, a manufacturing method of the negative electrode, and the lithium battery including the same. The carbon material layer of the negative electrode for the lithium battery has a crystalline structure. [Reference numerals] (AA) First cycle;(BB) Tenth cycle;(CC) Capacity (mAh)

Abstract translation: 本发明涉及一种锂电池用负极，其包含在金属层的表面上形成的板状结构的含有锂的金属层和碳材料层，负极的制造方法以及锂电池，其包括 一样。 用于锂电池的负极的碳材料层具有晶体结构。 （附图标记）（AA）第一循环;（BB）第十循环;（CC）容量（mAh）

公开(公告)号：KR1020130026078A

公开(公告)日：2013-03-13

申请号：KR1020110089462

申请日：2011-09-05

Applicant: 삼성전자주식회사

Inventor： 문지범 ,  김한수 ,  한승훈 ,  안원석 ,  김규용

IPC: H04N13/00

CPC classification number: H04N13/261

Abstract: PURPOSE: A content converting device and a content converting method thereof are provided to supply a user interface for improving the efficiency of work when a plurality of workers perform 2D-3D conversion work. CONSTITUTION: A content converting device displays a first work user interface for 2D-3D conversion work on a display unit(31). The content converting device enables a first worker to determine directions for the conversion work through the first user interface(32). The content converting device displays a second work user interface indicating the determined directions on the display unit(33). The content converting device enables the second worker to perform the conversion work through the second work user interface according to the directions(34). [Reference numerals] (31) Displaying a first work UI for 2D/3D contents conversion; (32) Determining directions for the conversion work by a first user using the first work UI; (33) Displaying a second work UI indicating the determined directions; (34) Performing the conversion work by a second user using the second work UI; (AA) Start; (BB) End

Abstract translation: 目的：提供一种内容转换装置及其内容转换方法，以在多个工作人员执行2D-3D转换工作时提供用于提高工作效率的用户界面。 规定：内容转换设备在显示单元（31）上显示用于2D-3D转换工作的第一工作用户界面。 内容转换装置使得第一工作人员能够通过第一用户界面（32）确定用于转换工作的方向。 内容转换装置在显示单元（33）上显示指示所确定的方向的第二工作用户界面。 内容转换装置使得第二工作人员能够根据方向（34）通过第二工作用户界面执行转换工作。 （31）显示用于2D / 3D内容转换的第一工作UI; （32）使用第一工作UI确定第一用户的转换工作的方向; （33）显示指示所确定的方向的第二工作UI; （34）使用第二工作UI执行第二用户的转换工作; （AA）开始; （BB）结束

公开(公告)号：KR1020130010733A

公开(公告)日：2013-01-29

申请号：KR1020110071549

申请日：2011-07-19

Applicant: 삼성전자주식회사 ,  한양대학교 산학협력단

Inventor： 최재만 ,  황승식 ,  권문석 ,  송민상 ,  손정국 ,  김명훈 ,  김한수 ,  백운규 ,  송태섭

IPC: H01M4/38 ,  B82B3/00 ,  H01M10/052 ,  H01M4/1395

CPC classification number: H01M10/0525 ,  H01M4/0428 ,  H01M4/0471 ,  H01M4/364 ,  H01M4/366 ,  H01M4/38 ,  H01M4/386 ,  H01M10/052 ,  H01M2004/021 ,  H01M2004/027 ,  Y02E60/122 ,  B82B3/00 ,  H01M4/134 ,  H01M4/1395 ,  H01M4/387

Abstract: PURPOSE: A negative electrode active material is provided to improve initial charging and discharging efficiency, capacity maintenance, and high voltage properties of a high capacity lithium battery by using multi-layered nanotubes. CONSTITUTION: A negative electrode active material comprises: an inner layer which comprises an inner surface of metal nanotubes, and an outer layer which comprises an outer surface of the metal nanotubes. The inner layer comprises a first metal of which an atomic number is 13 or more. The outer layer comprises multilayered metal nanotubes which comprise a second metal different with the first metal. The second metal has a lower resistivity than the resistivity of the first metal. The diffusivity of lithium ions is high and volume expansion at charging is low. [Reference numerals] (AA) Metal oxide nanorod; (BB) Conductive substrate; (CC) First metal coating; (DD) Metal oxide template etching; (EE) First metal nanotube; (FF) Second metal coating; (GG) First metal; (HH) Second metal; (II) Inner and outer layer structures

Abstract translation: 目的：提供一种负极活性材料，通过使用多层纳米管，提高高容量锂电池的初始充放电效率，容量维护和高电压特性。 构成：负极活性物质包括：包含金属纳米管的内表面的内层和包含金属纳米管的外表面的外层。 内层包含原子序数为13以上的第一金属。 外层包括多层金属纳米管，其包含与第一金属不同的第二金属。 第二金属具有比第一金属的电阻率更低的电阻率。 锂离子的扩散性高，充电时的体积膨胀低。 （标号）（AA）金属氧化物纳米棒; （BB）导电基板; （CC）第一金属涂层; （DD）金属氧化物模板蚀刻; （EE）第一金属纳米管; （FF）第二金属涂层; （GG）第一金属; （HH）第二金属; （二）内外层结构

公开(公告)号：KR1020120094338A

公开(公告)日：2012-08-24

申请号：KR1020110013780

申请日：2011-02-16

Applicant: 삼성전자주식회사

Inventor： 이재구 ,  김한수 ,  박영우 ,  정길수

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L23/52 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L27/0688 ,  H01L2924/00

Abstract: PURPOSE: A 3D semiconductor memory device and a manufacturing method thereof are provided to suppress the reduction of a cell current by preventing an electric field from being weakened in the lower side of a semiconductor pattern. CONSTITUTION: An electrode structure is arranged on the substrate and includes a top electrode and a bottom electrode. A semiconductor pattern(SP) passes through the electrode structure and is connected to the substrate. A vertical insulation layer(135) is interposed between the semiconductor pattern and the electrode structure. A bottom insulation layer(101) is interposed between the bottom of the vertical insulation layer and the upper side of the substrate.

Abstract translation: 目的：提供一种3D半导体存储器件及其制造方法，以通过防止半导体图案的下侧的电场减弱来抑制单元电流的降低。 构成：电极结构布置在衬底上并包括顶电极和底电极。 半导体图案（SP）通过电极结构并连接到基板。 在半导体图案和电极结构之间插入有垂直绝缘层（135）。 底部绝缘层（101）插入在垂直绝缘层的底部和基板的上侧之间。

公开(公告)号：KR1020110129256A

公开(公告)日：2011-12-01

申请号：KR1020100048795

申请日：2010-05-25

Applicant: 삼성전자주식회사

Inventor： 황성민 ,  김경훈 ,  김한수 ,  손병근 ,  심재주 ,  장재훈 ,  조원석 ,  조후성

IPC: H01L27/10 ,  H01L21/70 ,  H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/0688 ,  H01L21/76816 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/11551 ,  H01L27/11578

Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to stably supply voltage on a substrate through a pickup area which is electrically connected to the substrate, thereby making the semiconductor device with excellent reliability. CONSTITUTION: A substrate(100) is doped with a first conductive type dopant. A plurality of laminate structures is extended side by side to a first direction on the substrate. Each laminate structure comprises gate electrodes(157L,157,157U) which is laminated by being separated from each other on the substrate. A plurality of laminate structures comprises a pair of the laminate structures which is perpendicular to the first direction and separated with a first interval to a second direction. A pickup region(176) is extended to the first direction within the substrate between the pair of the laminated structures and doped with the first conductive type dopant.

Abstract translation: 目的：提供半导体器件及其制造方法，通过与基板电连接的拾取区域稳定地在基板上提供电压，从而使半导体器件具有良好的可靠性。 构成：衬底（100）掺杂有第一导电型掺杂剂。 多个层压结构在基板上沿第一方向并排延伸。 每个层压结构包括通过在基板上彼此分离而层压的栅电极（157L，157,157U）。 多个层叠结构包括一对垂直于第一方向并且以第一间隔分离成第二方向的层压结构。 拾取区域（176）在衬底之间的第一方向延伸到一对层压结构之间并掺杂有第一导电型掺杂剂。

公开(公告)号：KR1020110126999A

公开(公告)日：2011-11-24

申请号：KR1020100046593

申请日：2010-05-18

Applicant: 삼성전자주식회사

Inventor： 황성민 ,  김한수 ,  조원석 ,  장재훈 ,  심재주

IPC: H01L27/115 ,  H01L27/02

CPC classification number: H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: PURPOSE: A semiconductor device and a method of fabricating the same are provided to minimize an over etching due to the height difference between contact holes by forming a reserved contact hole through a barrier rip. CONSTITUTION: In a semiconductor device and a method of fabricating the same, a substrate(100) comprises a first area(10) and a second area(20). A pattern structure including each pattern(108) is arranged on the substrate within the first area. A conductive pattern(CP) is arranged on the substrate within the second area. The conductive patterns includes a connection unit connecting a plurality of gate electrodes and one end of a gate electrode. A semiconductor pillar(130) comprises a semiconductor(131), a filling insulating material(132), and a drain(133).

Abstract translation: 目的：提供一种半导体器件及其制造方法，以通过形成通过阻挡层的保留接触孔来最小化由于接触孔之间的高度差引起的过度蚀刻。 构成：在半导体器件及其制造方法中，衬底（100）包括第一区域（10）和第二区域（20）。 包括每个图案（108）的图案结构布置在第一区域内的基板上。 导电图案（CP）布置在第二区域内的基板上。 导电图案包括连接多个栅电极和栅电极的一端的连接单元。 半导体柱（130）包括半导体（131），填充绝缘材料（132）和漏极（133）。

公开(公告)号：KR1020110070142A

公开(公告)日：2011-06-24

申请号：KR1020090126854

申请日：2009-12-18

Applicant: 삼성전자주식회사

Inventor： 심재주 ,  김한수 ,  조원석 ,  장재훈 ,  조우진

IPC: H01L21/822 ,  H01L21/027 ,  H01L21/28

CPC classification number: H01L23/3157 ,  H01L21/76816 ,  H01L23/291 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  G03F7/0002 ,  G03F7/0037 ,  H01L2924/00

Abstract: PURPOSE: A three dimensional semiconductor device and manufacturing method thereof are provided to prevent deformation of a mold structure by sidewall molds, thereby obtaining structural stability without a separate support object. CONSTITUTION: A mold structure provides gap areas. The mold structure includes interlayer molds and sidewall molds. The interlayer molds(110) define the upper surface and the lower surface of wiring patterns. The sidewall molds(130) define sidewalls of the wiring patterns under the interlayer molds. A wiring structure comprises a plurality of wiring patterns arranged in the gap areas.

Abstract translation: 目的：提供一种三维半导体器件及其制造方法，以防止侧壁模具对模具结构的变形，从而在没有单独的支撑体的情况下获得结构稳定性。 规定：模具结构提供了间隙区域。 模具结构包括层间模具和侧壁模具。 层间模具（110）限定布线图案的上表面和下表面。 侧壁模具（130）限定层间模具下面的布线图案的侧壁。 布线结构包括布置在间隙区域中的多个布线图案。

公开(公告)号：KR1020110054361A

公开(公告)日：2011-05-25

申请号：KR1020090110975

申请日：2009-11-17

Applicant: 삼성전자주식회사

Inventor： 심선일 ,  허성회 ,  김한수 ,  장재훈 ,  조후성

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/02365 ,  H01L21/02697 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7841

Abstract: PURPOSE: A three dimensional semiconductor memory device is provided to operate at high speed and improve reliability by decreasing resistance between sub gates. CONSTITUTION: A substrate has a pair of sub cell regions and a cell array region including a strapping region. A plurality of sub gates(135a,135au,135b,135bu) are successively laminated in each sub cell region. Each sub gate has an extension unit which is extended in the strapping region. A vertical type channel pattern successively passes through the sub gates laminated in each sub cell region. The wirings are electrically connected to the extension units of the sub gates. Each wire is arranged in the pair of sub cell regions and is electrically connected to the extension units of the pair of sub gates on the same level.

Abstract translation: 目的：提供三维半导体存储器件，通过降低子门之间的电阻，高速运行并提高可靠性。 构成：衬底具有一对子电池区域和包括带状区域的电池阵列区域。 多个子门（135a，135au，135b，135bu）依次层叠在每个子单元区域中。 每个子门具有在捆扎区域中延伸的延伸单元。 垂直型通道图案依次通过层叠在每个子单元区域中的子门。 配线电连接到子门的延伸单元。 每根导线布置在一对子单元区域中，并且与同一电平上的一对子门的延伸单元电连接。

公开(公告)号：KR1020110029403A

公开(公告)日：2011-03-23

申请号：KR1020090087063

申请日：2009-09-15

Applicant: 삼성전자주식회사

Inventor： 심선일 ,  장재훈 ,  김한수 ,  황성민 ,  조원석 ,  임진수

IPC: H01L27/10 ,  H01L21/82

CPC classification number: H01L29/7926 ,  H01L27/11556 ,  H01L27/11582

Abstract: PURPOSE: A three dimensional semiconductor memory device and a manufacturing method thereof are provided to restrain the non-uniformity in the electrical characteristic between the memory cells by forming the lower and upper semiconductor patterns using the same material without discontinuous boundary. CONSTITUTION: A lower part thin film structure(100) is formed on a substrate(10). The lower part thin film structure comprises a plurality of bottom insulating layers(121~127) and a plurality of lower part sacrificing layers(131~136). A lower penetration hole(140) passes through the lower part thin film structure. A bottom semiconductor pattern(150) fills the lower penetration holes.

Abstract translation: 目的：提供三维半导体存储器件及其制造方法，以通过使用相同材料形成下部和上部半导体图案来不间断地限制存储单元之间的电气特性的不均匀性。 构成：在基板（10）上形成下部薄膜结构（100）。 下部薄膜结构包括多个底部绝缘层（121〜127）和多个下部牺牲层（131〜136）。 下穿孔（140）穿过下部薄膜结构。 底部半导体图案（150）填充下部穿透孔。