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公开(公告)号：KR1020120030816A
公开(公告)日：2012-03-29
申请号：KR1020100092583
申请日：2010-09-20
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5621 , G11C16/10 , G11C16/3404 , G11C16/06 , G11C11/5628 , G11C16/32
Abstract: PURPOSE: A flash memory and a self interleaving method thereof are provided to alleviate an imbalance of bit error rate using a self interleaving method. CONSTITUTION: A memory cell array(1110) which includes a plurality of physical pages stores a plurality of logical pages in each physical page. A self interleaver(1141) divides each logical page into a plurality of interleaving units. The self interleaver divides each interleaving unit into a plurality of sectors. The self interleaver performs an interleaving operation by mixing the sectors of the logical pages which are different from each other. A data input/output circuit(1120) stores the logical pages which are mixed to the physical page of the memory cell array.
Abstract translation: 目的：提供一种闪速存储器及其自交错方法，以便使用自交错方法来减轻误码率不平衡。 构成：包括多个物理页面的存储单元阵列（1110）在每个物理页面中存储多个逻辑页面。 自交织器（1141）将每个逻辑页划分成多个交织单元。 自交织器将每个交织单元划分成多个扇区。 自交织器通过混合彼此不同的逻辑页面的扇区来执行交织操作。 数据输入/输出电路（1120）存储与存储单元阵列的物理页面混合的逻辑页面。
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公开(公告)号：KR1020100107089A
公开(公告)日：2010-10-05
申请号：KR1020090025168
申请日：2009-03-25
Applicant: 삼성전자주식회사
CPC classification number: G06F11/1048
Abstract: PURPOSE: A storage device and a data storing system having the same are provided to differently form a storage area according to the property of data inputted from the outside by comprising two memories of different structures in the storage device. CONSTITUTION: A memory cell array(120) stores a first data(D1) or a second data(D2) offered from a controller unit(110). The memory cell array comprises a first memory(121) and a second memory(123). The first memory is formed in a charge trap flash structure. The second memory is formed in a floating gate structure.
Abstract translation: 目的：提供存储装置和具有该存储装置的数据存储系统，以通过包括存储装置中不同结构的两个存储器，根据从外部输入的数据的属性不同地形成存储区域。 构成：存储单元阵列（120）存储从控制器单元（110）提供的第一数据（D1）或第二数据（D2）。 存储单元阵列包括第一存储器（121）和第二存储器（123）。 第一存储器形成在电荷阱闪存结构中。 第二存储器形成为浮动栅极结构。
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公开(公告)号：KR1020100081551A
公开(公告)日：2010-07-15
申请号：KR1020090000842
申请日：2009-01-06
Applicant: 삼성전자주식회사
CPC classification number: H03M13/1111 , H03M13/1108 , H03M13/3707 , H03M13/451 , H03M13/458 , H04L1/0045 , H04L1/0057 , H03M13/3738 , H04L27/00 , H04W4/18
Abstract: PURPOSE: A decoding method and a memory system device for using the method are provided to improve decoding throughput by increasing the successful rate of a decoding operation while reducing an error-floor region. CONSTITUTION: Plural parameter nodes and plural check nodes are updated by using a provability value of the received data(S120). If the updating is not successful, at least one variable node is selected from the variable nodes. The provability value of the data received to the selected variable node is corrected. The variable nodes and the check nodes are updated by using probability values.
Abstract translation: 目的：提供一种使用该方法的解码方法和存储系统装置，通过增加解码操作的成功率同时减少误差区域来提高解码吞吐量。 构成：通过使用接收到的数据的可验证性值来更新多个参数节点和多个校验节点（S120）。 如果更新不成功，则从变量节点中选择至少一个变量节点。 修正接收到所选变量节点的数据的可验证性值。 通过使用概率值更新变量节点和校验节点。
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公开(公告)号：KR1020100013485A
公开(公告)日：2010-02-10
申请号：KR1020080075020
申请日：2008-07-31
Applicant: 삼성전자주식회사
CPC classification number: G11C16/349 , G11C11/5628 , G11C2211/5644
Abstract: PURPOSE: A memory device including a controller selecting a memory cell and a wear leveling method are provided to improve the durability of the memory cell by operating a wear leveling based on an elapsed time after the memory cell is erased. CONSTITUTION: A memory cell array(110) comprises a first memory cell and a second memory cell. A control unit(120) selects one of the first memory cell or the second memory cell. The programming unit(130) saves a data to the memory cell. The control unit generates a first parameter based on an elapsed time after the first memory cell is erased and the number of times which the first memory cell is erased. The control unit generates a second parameter based on an elapsed time after the second memory cell is erased and the number of times which the second memory cell is erased.
Abstract translation: 目的：提供包括选择存储单元的控制器和磨损均衡方法的存储器件，以通过基于擦除存储器单元之后的经过时间进行磨损均衡来提高存储器单元的耐久性。 构成：存储单元阵列（110）包括第一存储单元和第二存储单元。 控制单元（120）选择第一存储单元或第二存储单元中的一个。 编程单元（130）将数据保存到存储单元。 控制单元基于擦除第一存储单元之后的经过时间和第一存储单元被擦除的次数来生成第一参数。 控制单元基于在擦除第二存储单元之后的经过时间和第二存储单元被擦除的次数来生成第二参数。
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公开(公告)号：KR1020090123658A
公开(公告)日：2009-12-02
申请号：KR1020080049830
申请日：2008-05-28
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G11C11/5628 , G11C2211/5621
Abstract: PURPOSE: A memory device and a memory programming method are provided to reduce a width of dissemination of threshold voltage of a memory cell by using a programming part and a controller. CONSTITUTION: A memory cell array(110) comprises a plurality of memory cells. A programming part(120) applies a plurality of pulses corresponding to program voltage to a gate terminal of each memory cell. The programming part applies program condition voltage to a bit line connected to a memory cell having threshold voltage lower than verification voltage among the memory cells. The programming part stores data in each memory cell by varying the threshold voltage of each memory cell. A controller(130) increases the program voltage at each pulse as much as a first increment during a first time interval. The controller increases the program voltage at each pulse as much as a second increment during a second time interval. An identification unit(140) identifies the memory cell having the threshold voltage lower than the verification voltage among the memory cells.
Abstract translation: 目的：提供存储器件和存储器编程方法，以通过使用编程部件和控制器来减小存储器单元的阈值电压的传播宽度。 构成：存储单元阵列（110）包括多个存储单元。 编程部件（120）将对应于编程电压的多个脉冲施加到每个存储器单元的栅极端子。 编程部分将编程条件电压应用于与存储单元中具有低于验证电压的阈值电压的存储单元连接的位线。 编程部分通过改变每个存储单元的阈值电压将数据存储在每个存储单元中。 控制器（130）在第一时间间隔期间将每个脉冲处的编程电压增加多达第一增量。 控制器在第二时间间隔期间将每个脉冲处的编程电压增加多达第二增量。 识别单元（140）识别具有低于存储器单元中的验证电压的阈值电压的存储单元。
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Patent Agency Ranking
公开(公告)号：KR1020090123656A
公开(公告)日：2009-12-02
申请号：KR1020080049828
申请日：2008-05-28
Applicant: 삼성전자주식회사
CPC classification number: G11C16/3454 , G11C11/5628 , G11C2211/5621
Abstract: PURPOSE: A memory device and a memory programming method are provided to reduce errors in a process of reading data from a memory cell by using a new programming method. CONSTITUTION: A memory cell array(110) comprises a plurality of memory cells. A controller(120) extracts status information of each of the plural memory cells. The controller partitions the plural memory cells into a first group and a second group based on the extracted status information. The controller assigns first verification voltage to memory cells of the first group. The controller assigns second verification voltage to memory cells of the second group. A programming part(130) changes threshold values of the memory cells of the first and second groups.
Abstract translation: 目的：提供存储器件和存储器编程方法，以通过使用新的编程方法来减少从存储器单元读取数据的过程中的错误。 构成：存储单元阵列（110）包括多个存储单元。 控制器（120）提取多个存储单元中的每一个的状态信息。 控制器基于所提取的状态信息将多个存储单元划分成第一组和第二组。 控制器将第一验证电压分配给第一组的存储单元。 控制器将第二验证电压分配给第二组的存储单元。 编程部分（130）改变第一和第二组的存储器单元的阈值。
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公开(公告)号：KR100750164B1
公开(公告)日：2007-08-21
申请号：KR1020060015630
申请日：2006-02-17
Applicant: 삼성전자주식회사
IPC: H04N21/431
Abstract: An apparatus and a method for providing a three-dimensional EPG(electronic programming guide) are provided to allow a user to conveniently and intuitionally search for broadcasting program information included in the EPG. An EPG screen configuring unit(140) configures an EPG screen such that broadcasting program information is displayed on at least three faces of a three-dimensional polyhedron. A controlling unit(130) controls the EPG screen configuring unit(140) to configure the EPG screen such that broadcasting program information about another broadcasting time zone or another broadcasting channel is displayed on the EPG screen based on a user input signal requesting a search for the broadcasting program information about another broadcasting time zone or another broadcasting channel.
Abstract translation: 提供了一种用于提供三维EPG（电子节目指南）的设备和方法，以允许用户方便且直观地搜索包含在EPG中的广播节目信息。 EPG屏幕配置单元（140）配置EPG屏幕，使得广播节目信息显示在三维多面体的至少三个面上。 控制单元（130）控制EPG屏幕配置单元（140）以配置EPG屏幕，使得基于请求搜索的EPG屏幕在EPG屏幕上显示关于另一广播时间段或另一广播频道的广播节目信息 关于另一个广播时间段或另一个广播频道的广播节目信息。
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公开(公告)号：KR100734299B1
公开(公告)日：2007-07-02
申请号：KR1020050135874
申请日：2005-12-30
Applicant: 삼성전자주식회사
Inventor： 김용준
IPC: G11C5/14
Abstract: A current sensing type internal voltage generating circuit is provided to generate a stable internal voltage with fast operation speed by using the scheme of sensing a current, rather than sensing a voltage. A current sense amplification circuit(51) receives the current of a reference voltage and the current of an internal voltage, and then senses the current difference and outputs an output voltage and a complementary output voltage corresponding to the current difference. A voltage sense amplification circuit(53) generates a driving voltage by sensing the voltage difference between the output voltage and the complementary output voltage. A driver(P51) generates an internal voltage in response to the driving voltage.
Abstract translation: 提供一种电流感测型内部电压产生电路，通过使用感测电流的方案而不是感测电压来产生具有快速操作速度的稳定内部电压。 电流感测放大电路（51）接收参考电压的电流和内部电压的电流，然后感测电流差并输出对应于电流差的输出电压和互补输出电压。 电压读出放大电路（53）通过感测输出电压与互补输出电压之间的电压差来产生驱动电压。 驱动器（P51）响应驱动电压产生内部电压。
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公开(公告)号：KR1020060023775A
公开(公告)日：2006-03-15
申请号：KR1020040072630
申请日：2004-09-10
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L23/5389 , G01L19/146 , H01L23/5387 , H01L24/24 , H01L2224/24051 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , H05K1/185 , H05K1/189 , H01L2924/00
Abstract: 유연소자, 유연압력센서, 및 이들의 제조방법이 제공된다. 본 유연소자는, 유연한 물질로 제작되어 유연성을 갖는 제1 유연기판, 소정 두께로 제작되어 유연성을 가지며 제1 유연기판 위에 부착되는 능동소자 및 유연한 물질로 제작되어 유연성을 가지며 능동소자 위에 증착되는 제2 유연기판을 포함한다. 본 발명에 따른, 유연소자와 유연압력센서는 높은 유연성을 가지기 때문에, 생명체, 인체 등에 이식되어 의료용으로 사용될 수 있고, 곡면에도 삽입가능하므로, 반도체 패키지소자가 삽입될 수 있는 공간상의 제약을 허물수 있는데 기여한다.
유연성, 능동소자, 유연기판, 압력센서-
公开(公告)号：KR100385976B1
公开(公告)日：2003-06-02
申请号：KR1020000065256
申请日：2000-11-03
Applicant: 삼성전자주식회사
IPC: H05K3/02
CPC classification number: H01P3/088 , H05K1/024 , H05K2201/0394 , H05K2201/09845 , H05K2201/2036
Abstract: A circuit board having a dielectric substrate, a grounding surface formed on at least one surface of the dielectric substrate, and transmission lines formed on one surface of the dielectric substrate for transmitting electrical signals. At least a portion of each of the transmission lines is isolated from an upper surface of the dielectric substrate to reduce the effective permittivity between the transmission lines and the grounding surface and a dielectric loss therebetween. In a method of manufacturing a circuit board, first, a sacrificial layer is formed on a dielectric substrate. Next, supporter patterns and transmission line patterns are formed by patterning the sacrificial layer. Then, supporters and transmission lines are formed in the supporter patterns and transmission line patterns, respectively. Following this, the sacrificial layer is removed so that the transmission lines are isolated from the upper surface of the dielectric substrate. Thereafter, a grounding surface is formed on at least one surface of the dielectric substrate.
Abstract translation: 一种电路板，其具有电介质基板，在电介质基板的至少一个表面上形成的接地表面以及形成在电介质基板的一个表面上的用于传输电信号的传输线。 每个传输线的至少一部分与介质基底的上表面隔离，以降低传输线与接地表面之间的有效介电常数和介电损耗。 在制造电路板的方法中，首先，在电介质基板上形成牺牲层。 接下来，通过图案化牺牲层来形成支撑图案和传输线图案。 然后，分别在支持者图案和传输线图案中形成支持者和传输线。 在此之后，去除牺牲层，使得传输线与电介质衬底的上表面隔离。 之后，在电介质基板的至少一个表面上形成接地表面。
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