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公开(公告)号：KR1019930003991B1
公开(公告)日：1993-05-19
申请号：KR1019900021844
申请日：1990-12-26
Applicant: 한국전자통신연구원
Abstract: The device for maintaining the cash consistency in multiple processor systems comprises: a snoop memory data path setter (13), which makes the write back signal and the update signal according to the contents of snoop memory as well as the input state of cash memory; a system bus watcher (11), which makes the control signal according to the output signal of the setter (13); a snoop memory controller (14), which makes the write signal of the snoop state memory and the snoop tag memory; a snoop requester (12) requesting the use of system bus to the system bus watcher.
Abstract translation: 用于维持多处理器系统中的现金一致性的装置包括：窥探存储器数据路径设置器（13），其根据窥探存储器的内容以及现金存储器的输入状态产生回写信号和更新信号; 系统总线监视器（11），其根据所述设定器（13）的输出信号进行所述控制信号; 窥探存储器控制器（14），其产生窥探状态存储器和窥探标签存储器的写入信号; 窥探请求者（12）请求系统总线使用到系统总线监视器。
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公开(公告)号：KR1019920010969B1
公开(公告)日：1992-12-26
申请号：KR1019900021855
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F12/08
Abstract: The circuit optimally shares one cache memory to improve the efficiency of the cache memory when a snooper and a CPU simultaneously use the memory. The circuit includes an approach controller of processor (11) for interfacing the data needed to approach a CPU cache (4) or a CPU (1), an approach controller of snooper (12), a memory controller of cache data (13) for controlling the data state of a cache memory (6) according to the control signals from the two approach controllers (11,12), and a cache controller (3) composed of the 1st cue (Fc;14) and the 2nd cue (Fs;15).
Abstract translation: 当窥探者和CPU同时使用存储器时，电路最佳地共享一个高速缓冲存储器以提高高速缓冲存储器的效率。 该电路包括处理器（11）的接近控制器，用于将接近CPU高速缓存（4）或CPU（1）所需的数据，窥探者（12）的接近控制器，高速缓存数据（13）的存储器控制器 根据来自两个进场控制器（11,12）的控制信号，控制高速缓冲存储器（6）的数据状态，以及由第一提示（Fc; 14）和第二提示（Fs）组成的高速缓存控制器（3） ; 15）。
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公开(公告)号：KR1019920010968B1
公开(公告)日：1992-12-26
申请号：KR1019900021854
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F12/08
Abstract: The circuit controls address path in a copyback and writeback mode effectively. The circuit includes a comparator (11) for generating retry signal by comparing input and output address signals with each other, a CPU cache address path former (12) for generating cache state memory (6b) address and cache tag memory (6a) address according to address signal transmitted from a CPU, a snoop cache address path former (13) for generating snoop state memory (6d) address and snoop tag memory (6c) address, a data cache address path former (14) for transmitting address signals to a data memory, and a system address bus generator (15) for transmitting address signals to a system bus controller (2) according to address signals transmitted from the cache address path former (12) and the snoop cache address former (13).
Abstract translation: 电路有效地控制了回写和回写模式下的地址路径。 该电路包括用于通过比较输入和输出地址信号而产生重试信号的比较器（11），用于产生高速缓存状态存储器（6b）地址和高速缓存标签存储器（6a）地址的CPU高速缓存地址路径形成器（12） 寻址从CPU发送的信号，用于产生窥探状态存储器（6d）地址和窥探标签存储器（6c）地址）的窥探缓存地址路径形成器（13），用于将地址信号发送到 数据存储器和系统地址总线发生器（15），用于根据从高速缓存地址路径形成器（12）和窥探缓存地址生成器（13）发送的地址信号，将地址信号发送到系统总线控制器（2）。
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公开(公告)号：KR1019920010967B1
公开(公告)日：1992-12-26
申请号：KR1019900021847
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F12/08
Abstract: The control circuit for requesting the use of the system bus from an external bus arbitrator with controlling the cache memory using a copy back mode according to the processor operation comprises a cache change data generator (13) for generating control signals according to the contents of a cache tag memory and a cache state memory to change the state of the cache state memory, a processor interface unit (11) for receiving the control signal from the generator (13) to halt or retry a CPU, a cache memory change signal generator (14) for transmitting a write signal to the cache state memory and cache tag memory, and a system bus request unit (12), thereby synchronizing the signals of the control circuits with the main clock to minimize the skew generation at the output stage.
Abstract translation: 根据处理器操作，通过使用复制模式控制高速缓冲存储器的外部总线仲裁器请求使用系统总线的控制电路包括：高速缓存改变数据生成器（13），用于根据处理器操作的内容生成控制信号 高速缓存标签存储器和高速缓存状态存储器以改变高速缓存状态存储器的状态;处理器接口单元（11），用于从发生器（13）接收控制信号以停止或重试CPU;高速缓存存储器改变信号发生器（ 14），用于将写入信号发送到高速缓存状态存储器和高速缓存标签存储器，以及系统总线请求单元（12），从而使控制电路的信号与主时钟同步，以使输出级的偏斜产生最小化。
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Patent Agency Ranking
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公开(公告)号：KR1019920003287B1
公开(公告)日：1992-04-27
申请号：KR1019900002222
申请日：1990-02-22
Applicant: 한국전자통신연구원
IPC: G06F13/16
Abstract: The circuit includes a D flip-flop (FF) for receiving bus data responding signals and bus error signals from a NAND gate (N1) through a clock terminal (CK). The output of the D flip-flop (FF) is supplied to first and second shifters (S1)(S2), and store enable signals which are the output signals of the first and second shifters (S1)(S2) are supplied through a NAND gate (N2), while chip selecting signals which are the output of the first and second shifters (S1)(S2) are supplied through a NOR gate (NOR) and a buffer (B). The NAND gate (N4) receives pre-set signals, and supplies its output to a clear terminal (CLR) of the D flip-flop (FF).
Abstract translation: 电路包括用于通过时钟端子（CK）从NAND门（N1）接收总线数据响应信号和总线误差信号的D触发器（FF）。 D触发器（FF）的输出被提供给第一和第二移位器（S1）（S2），并且存储作为第一和第二移位器（S1）（S2）的输出信号的使能信号通过 NAND门（N2）通过NOR门（NOR）和缓冲器（B）提供作为第一和第二移位器（S1）（S2）的输出的片选信号。 NAND门（N4）接收预置信号，并将其输出提供给D触发器（FF）的清零端（CLR）。
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公开(公告)号：KR1019900003751B1
公开(公告)日：1990-05-31
申请号：KR1019870006241
申请日：1987-06-19
Applicant: 한국전자통신연구원
IPC: G06F13/20
Abstract: A microprocessor, RAM, ROM, trigger control logic (TCL), a trace control logic (TRCL), trace memory (TR-M), terminal interface logic (TIL) are connected through a local bus in one board. The TRCL, TR-M, and TIL are connected to a backplane bus thrugh a bus interface logic (BIL) and the TIL is connected to a general terminal (G-TM). When the user enters the command for information search or storage through the terminal, the microprocessor compares the backplane bus information coming through the BIL with the trigger condition of the TCL and the TRCL stores the information into the TR-M during the preset bus cycle if the conditions are matched with each other.
Abstract translation: 微处理器，RAM，ROM，触发控制逻辑（TCL），跟踪控制逻辑（TRCL），跟踪存储器（TR-M），终端接口逻辑（TIL）通过一个板上的本地总线连接。 TRCL，TR-M和TIL通过总线接口逻辑（BIL）连接到背板总线，TIL连接到通用终端（G-TM）。 当用户通过终端输入信息搜索或存储命令时，微处理器将通过BIL的背板总线信息与TCL的触发条件进行比较，TRCL在预置的总线周期内将信息存储到TR-M中，如果 条件相互匹配。
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