公开(公告)号：WO2004042809A1

公开(公告)日：2004-05-21

申请号：PCT/US2003/033965

申请日：2003-10-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KAMMLER, Thorsten ,  WIECZOREK, Karsten ,  LENSKI, Markus

IPC: H01L21/285

CPC classification number: H01L21/28518 ,  H01L21/26506

Abstract: In highly sophisticated MOS transistors including nickel silicide portions (311) for reducing the silicon sheet resistance, nickel silicide stingers may lead to short circuits between the drain and source region and the channel region, thereby significantly lowering production yield. By substantially amorphizing corresponding portions (331) of the source and drain regions, the creation of clustered point defects may effectively be avoided during curing implantation induced damage, wherein a main diffusion path for nickel during the nickel silicide formation is interrupted. Thus, nickel silicide stingers may be significantly reduced or even completely avoided.

Abstract translation: 在包括用于降低硅片电阻的硅化镍部分（311）的高度复杂的MOS晶体管中，硅化镍烙铁可能导致漏极和源极区域和沟道区域之间的短路，从而显着降低产量。 通过使源极和漏极区域的对应部分（331）基本非晶化，可以在固化植入诱导的损伤期间有效地避免产生聚集点缺陷，其中在镍硅化物形成期间镍的主扩散路径被中断。 因此，可以显着降低或甚至完全避免硅化镍刺痛。

公开(公告)号：WO2004023533A3

公开(公告)日：2004-03-18

申请号：PCT/US2003/027366

申请日：2003-08-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： LUNING, Scott ,  WIECZOREK, Karsten ,  KAMMLER, Thorsten

IPC: H01L21/336

Abstract: An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).

公开(公告)号：EP1668681A1

公开(公告)日：2006-06-14

申请号：EP04784756.1

申请日：2004-09-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KAMMLER, Thorsten ,  WIECZOREK, Karsten ,  FRENKEL, Austin

IPC: H01L21/285

CPC classification number: H01L21/28518 ,  H01L21/28052 ,  H01L29/665

Abstract: By forming a buried nickel silicide layer (260A) followed by a cobalt silicide layer (261A) in silicon containing regions, such as a gate electrode of a field effect transistor, the superior characteristics of both silicides may be combined so as to provide the potential for further device scaling without unduly compromising the sheet resistance and the contact resistance of scaled silicon circuit features.

公开(公告)号：EP1649506A1

公开(公告)日：2006-04-26

申请号：EP04754333.5

申请日：2004-06-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  FEUDEL, Thomas ,  KAMMLER, Thorsten ,  BUCHHOLTZ, Wolfgang

IPC: H01L21/336 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/78618

Abstract: By forming an implantation mask (220) prior to the definition of the drain and the source areas (208), an effective decoupling of the gate dopant concentration from that of the drain and source concentrations is achieved. Moreover, after removal of the implantation mask (220), the lateral dimension of the gate electrode (205) may be defined by well-established sidewall spacer (207) techniques, thereby providing a scaling advantage with respect to conventional approaches based on photolithography and anisotropic etching.