公开(公告)号：WO2007126907A1

公开(公告)日：2007-11-08

申请号：PCT/US2007/007705

申请日：2007-03-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  FEUDEL, Thomas ,  HORSTMANN, Manfred ,  WIECZOREK, Karsten ,  HELLER, Thomas

Inventor： FEUDEL, Thomas ,  HORSTMANN, Manfred ,  WIECZOREK, Karsten ,  HELLER, Thomas

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/04

CPC classification number: H01L21/84 ,  H01L21/76251 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/7842

Abstract: By forming bulk-like transistors (151B) in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by providing transistors of increased transistor width or by providing body ties. Hence, the benefit of high switching speed may be maintained in speed-critical circuitry, such as CPU cores, while at the same time the RAM circuit may be formed in a highly space-efficient manner.

Abstract translation: 通过在其它SOI基CMOS电路的敏感RAM区域中形成块状晶体管（151B），可以实现有价值的芯片面积的显着节省，因为可以基于体晶体管配置形成RAM区域，从而消除滞后 通常可以通过提供增加晶体管宽度的晶体管或通过提供身体纽带来考虑效果。 因此，高速切换速度的好处可以保持在诸如CPU内核之类的速度关键电路中，同时可以以高空间效率的方式形成RAM电路。

公开(公告)号：WO2007018780A1

公开(公告)日：2007-02-15

申请号：PCT/US2006/024680

申请日：2006-06-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  CRAIG, Mark ,  WIECZOREK, Karsten ,  HORSTMANN, Manfred

Inventor： CRAIG, Mark ,  WIECZOREK, Karsten ,  HORSTMANN, Manfred

IPC: H01L27/11

CPC classification number: H01L29/7843 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/78

Abstract: SRAM devices utilizing tensile-stressed strain films and methods for fabricating such SRAM devices are provided. An SRAM device (50), in one embodiment, comprises an NFET (54) and a PFET (52) that are electrically coupled and physically isolated. The PFET (52) has a gate region (64), a source region (60), and a drain region (58). A tensile-strained stress film (76) is disposed on the gate region (64) and at least a portion of the source region (60) and the drain region (58) of the PFET (52). A method for fabricating a cell of an SRAM device (50) comprises fabricating an NFET (54) and a PFET (52) overlying a substrate (56). The PFET (52) and the NFET (54) are electrically coupled and are physically isolated. A tensile-strained stress film (76) is deposited on the gate region (64) and at least a portion of the source region (60) and the drain region (58) of the PFET (52).

Abstract translation: 提供了使用拉伸应力应变膜的SRAM器件和制造这种SRAM器件的方法。 在一个实施例中，SRAM器件（50）包括电耦合和物理隔离的NFET（54）和PFET（52）。 PFET（52）具有栅极区（64），源极区（60）和漏极区（58）。 拉伸应变膜（76）设置在栅极区域（64）上以及PFET（52）的源极区域（60）和漏极区域（58）的至少一部分。 一种用于制造SRAM器件（50）的单元的方法包括制造覆盖在衬底（56）上的NFET（54）和PFET（52）。 PFET（52）和NFET（54）电耦合并且物理隔离。 在栅极区域（64）和PFET（52）的源极区域（60）和漏极区域（58）的至少一部分上沉积拉伸应变膜（76）。

公开(公告)号：WO2004032217A1

公开(公告)日：2004-04-15

申请号：PCT/US2003/029031

申请日：2003-09-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  KAMMLER, Thorsten ,  HORSTMANN, Manfred

IPC: H01L21/285

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/66507 ,  H01L29/6653

Abstract: The introduction of a barrier diffusion material, such as nitrogen, into a silicon-containing conductive region, for example the drain and source regions (204, 205) and the gate electrode (208) of a field effect transistor, allows the formation of nickel silicide (211, 212), which is substantially thermally stable up to temperatures of 500 °C. Thus, the device performance may significantly improve as the sheet resistance of nickel silicide is significantly less than that of nickel disilicide.

Abstract translation: 诸如氮的阻挡扩散材料引入含硅导电区域，例如场效应晶体管的漏极和源极区域（204,205）和栅电极（208），允许形成镍 硅化物（211,212），其在500℃的温度下基本上是热稳定的。 因此，随着硅化镍的薄层电阻显着小于二硅化镍的电阻，器件性能可能显着提高。

公开(公告)号：WO2009108370A1

公开(公告)日：2009-09-03

申请号：PCT/US2009/001287

申请日：2009-02-27

Applicant: ADVANCED MICRO DEVICES, INC. ,  WIECZOREK, Karsten ,  HORSTMANN, Manfred ,  HUEBLER, Peter ,  RUTTLOFF, Kerstin

Inventor： WIECZOREK, Karsten ,  HORSTMANN, Manfred ,  HUEBLER, Peter ,  RUTTLOFF, Kerstin

IPC: H01L21/768 ,  H01L21/8238

CPC classification number: H01L21/76826 ,  H01L21/76832 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L29/7843 ,  Y02P80/30

Abstract: In a dual stress liner approach, an intermediate etch stop material (234) may be provided on the basis of a plasma-assisted oxidation process (250) rather than by deposition so the corresponding thickness (234T) of the etch stop material (234) may be reduced. Consequently, the resulting aspect ratio may be less pronounced compared to conventional strategies, thereby reducing deposition-related irregularities which may translate into a significant reduction of yield loss, in particular for highly scaled semiconductor devices (200).

Abstract translation: 在双重应力衬里方法中，可以基于等离子体辅助氧化工艺（250）而不是通过沉积来提供中间蚀刻停止材料（234），使得蚀刻停止材料（234）的对应厚度（234T） 可能会减少。 因此，与常规策略相比，所产生的纵横比可能不那么明显，从而减少沉积相关的不规则性，这可能转化为产量损失的显着降低，特别是对于高度缩放的半导体器件（200）。

公开(公告)号：WO2006118787A1

公开(公告)日：2006-11-09

申请号：PCT/US2006/014628

申请日：2006-04-19

Applicant: ADVANCED MICRO DEVICES, INC. ,  WIECZOREK, Karsten ,  RAAB, Michael ,  ROMERO, Karla

Inventor： WIECZOREK, Karsten ,  RAAB, Michael ,  ROMERO, Karla

IPC: H01L21/8234

CPC classification number: H01L21/823462

Abstract: By locally adapting the blocking capability of gate insulation layers 205A, 205B for N-channel transistors and P-channel transistors, the reliability and threshold stability of the P-channel transistor may be enhanced, while nevertheless electron mobility of the N-channel transistor may be kept at a high level. This may be accomplished by incorporating a different amount of a dielectric dopant into respective gate insulation layer portions 205A, 205B.

Abstract translation: 通过局部地适应用于N沟道晶体管和P沟道晶体管的栅极绝缘层205A，205B的阻挡能力，可以提高P沟道晶体管的可靠性和阈值稳定性，而N沟道晶体管的电子迁移率可能 保持在高水平。 这可以通过将不同量的电介质掺杂剂并入相应的栅极绝缘层部分205A，205B中来实现。

公开(公告)号：WO2003083936A1

公开(公告)日：2003-10-09

申请号：PCT/US2002/040806

申请日：2002-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  KAHLERT, Volker ,  HORSTMANN, Manfred

IPC: H01L21/768

CPC classification number: H01L21/28518 ,  H01L21/28052 ,  H01L21/76841 ,  H01L29/4933 ,  H01L29/665

Abstract: A layer stack (220) comprising at least three material layers (221, 222, and 223) is provided on a silicon-containing conductive region to form a silicide portion (208) on and in the silicon-containing conductive region, wherein the layer (221) next to the silicon provides the metal atoms for the silicide reaction, the intermediate layer (222) is a metal-nitrogen-compound formed by supplying a nitrogen containing as during deposition, and for formation of the top layer (223), supply for said gas is discontinued. The method may be carried out as an in situ method, thereby significantly improving throughput and deposition tool performance compared to typical prior art processes, in which at least two deposition chambers have to be used

Abstract translation: 包含至少三个材料层（221,222和223）的层叠体（220）设置在含硅导电区域上以在含硅导电区域上和之中形成硅化物部分（208），其中层 （221）提供了用于硅化物反应的金属原子，中间层（222）是通过在沉积期间提供含氮并形成顶层（223）而形成的金属氮化合物， 所述气体的供给被停止。 该方法可以作为原位方法进行，从而与典型的现有技术方法相比显着提高生产量和沉积工具性能，其中必须使用至少两个沉积室

公开(公告)号：WO2003073491A1

公开(公告)日：2003-09-04

申请号：PCT/US2002/040807

申请日：2002-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  GRAETSCH, Falk ,  KRUEGEL, Stephan

IPC: H01L21/311

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

Abstract: A method of forming oxide layers of different thickness on a substrate (1) is disclosed, wherein the oxide layers preferably serve as gate insulation layers of field effect transistors. The method allows to form very thin, high quality oxide layers with a reduced number of masking steps compared to the conventional processing, wherein the thickness difference can be maintained within a range of some tenths of a nanometer. The method substantially eliminates any high temperature oxidations and is also compatible with most chemical vapor deposition techniques used for gate dielectric deposition in sophisticated semiconductor devices

Abstract translation: 公开了一种在基板（1）上形成不同厚度的氧化物层的方法，其中氧化物层优选用作场效应晶体管的栅极绝缘层。 与常规处理相比，该方法允许形成具有减少数量的掩模步骤的非常薄的高质量氧化物层，其中厚度差可以保持在十分之几纳米的范围内。 该方法基本上消除了任何高温氧化，并且也与用于复杂半导体器件中的栅极介电沉积的大多数化学气相沉积技术相兼容

公开(公告)号：WO2005034225A1

公开(公告)日：2005-04-14

申请号：PCT/US2004/031037

申请日：2004-09-17

Applicant: ADVANCED MICRO DEVICES, INC. ,  KAMMLER, Thorsten ,  WIECZOREK, Karsten ,  FRENKEL, Austin

Inventor： KAMMLER, Thorsten ,  WIECZOREK, Karsten ,  FRENKEL, Austin

IPC: H01L21/285

CPC classification number: H01L21/28518 ,  H01L21/28052 ,  H01L29/665

Abstract: By forming a buried nickel silicide layer (260A) followed by a cobalt silicide layer (261A) in silicon containing regions, such as a gate electrode of a field effect transistor, the superior characteristics of both silicides may be combined so as to provide the potential for further device scaling without unduly compromising the sheet resistance and the contact resistance of scaled silicon circuit features.

Abstract translation: 通过在含硅区域（例如场效应晶体管的栅电极）中形成掩埋的硅化镍层（260A），随后是硅化钴层（261A），可以组合两种硅化物的优异特性以提供电位 用于进一步的器件定标，而不会不适当地损害比例硅电路特征的薄层电阻和接触电阻。

公开(公告)号：WO2004095561A1

公开(公告)日：2004-11-04

申请号：PCT/US2003/041186

申请日：2003-12-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  GRAETSCH, Falk ,  HERRMANN, Lutz

IPC: H01L21/3115

CPC classification number: H01L21/28202 ,  H01L21/28158 ,  H01L21/28167 ,  H01L21/3144 ,  H01L29/518

Abstract: The present invention provides a technique for forming extremely thin insulation layers requiring the incorporation of specified amounts of nitrogen, wherein the effect of nitrogen variations across the substrate surface may be reduced in that during and/or after the nitrogen incorporation an oxidation process is performed. The nitrogen variations lead to a nitrogen concentration dependent oxidation rate and, hence, a nitrogen concentration dependent thickness variation of the insulating layer. In particular, the threshold variations of transistors including the thin insulating layer as a gate insulation layer may effectively be reduced.

Abstract translation: 本发明提供了一种形成极薄绝缘层的技术，该绝缘层需要结合规定量的氮，其中可以减少跨越衬底表面的氮变化的影响，因为在氮掺入期间和/或之后进行氧化过程。 氮变化导致氮浓度依赖的氧化速率，因此导致绝缘层的氮浓度依赖性厚度变化。 特别地，可以有效地降低包括作为栅极绝缘层的薄绝缘层的晶体管的阈值变化。

公开(公告)号：WO2004021440A1

公开(公告)日：2004-03-11

申请号：PCT/US2003/027367

申请日：2003-08-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  BURBACH, Gert ,  FEUDEL, Thomas

IPC: H01L27/06

CPC classification number: H01L28/40 ,  H01L27/0629 ,  H01L27/0805

Abstract: A semiconductor device comprises a field effect transistor (250) and a passive capacitor (240), wherein the dielectric layer (221a) of the capacitor (240) is comprised of a high-k material, whereas the gate insulation layer (231) of the field effect transistor (250) is formed of an ultra thin oxide layer or oxynitride layer so as to provide for superior carrier mobility at the interface between the gate insulation layer and the underlying channel region. Since carrier mobility in the capacitor is not of great importance, the high-k material allows the provision of high capacitance per unit area while featuring a thickness sufficient to effectively reduce leakage current.

Abstract translation: 半导体器件包括场效应晶体管（250）和无源电容器（240），其中电容器（240）的电介质层（221a）由高k材料构成，而栅极绝缘层（231）由 场效应晶体管（250）由超薄氧化物层或氮氧化物层形成，以便在栅极绝缘层和下面的沟道区域之间的界面处提供优异的载流子迁移率。 由于电容器中的载流子迁移率不是很重要，所以高k材料允许提供每单位面积的高电容，同时具有足以有效减少泄漏电流的厚度。