公开(公告)号：GB2483763B

公开(公告)日：2013-01-09

申请号：GB201115481

申请日：2011-09-08

Applicant: APPLE INC

Inventor： BISWAS SUKALPA ,  CHEN HAO ,  WADHAWAN RUCHI

IPC: G06F13/18

Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

公开(公告)号：HK1168672A1

公开(公告)日：2013-01-04

申请号：HK12109346

申请日：2012-09-21

Applicant: APPLE INC

Inventor： BISWAS SUKALPA ,  CHEN HAO ,  WADHAWAN RUCHI

IPC: G06F20060101

Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

公开(公告)号：NL2007411C2

公开(公告)日：2012-05-09

申请号：NL2007411

申请日：2011-09-14

Applicant: APPLE INC

Inventor： BISWAS SUKALPA ,  CHEN HAO ,  WADHAWAN RUCHI

IPC: G06F12/00 ,  G06F13/18

Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

公开(公告)号：NL2007411C

公开(公告)日：2012-05-09

申请号：NL2007411

申请日：2011-09-14

Applicant: APPLE INC

Inventor： BISWAS SUKALPA ,  CHEN HAO ,  WADHAWAN RUCHI

IPC: G06F12/00 ,  G06F13/18

CPC classification number: G06F13/1642 ,  G06F13/1626