公开(公告)号：BR112012024958A2

公开(公告)日：2016-07-12

申请号：BR112012024958

申请日：2011-05-26

Applicant: APPLE INC

Inventor： LILLY BRIAN P ,  CHEN HAO ,  KASSOFF JASON M

IPC: G06F13/16

Abstract: encaminhamento de palavra crítica com previsão adaptativa. a presente invenção refere-se a uma modalidade, um sistema que inclui um controlador de memória, processadores e caches correspondentes. o sistema pode incluir fontes de incerteza que impedem a organização precisa do encaminhamento de dados para uma operação de carga que não falta no cache do processador. o controlador de memória pode prover uma resposta antecipada que indica que os dados devem ser providos em um ciclo de clock subsequente. uma unidade de interface entre o controlador de memória e os caches/processadores pode prever um atraso a partir de uma resposta antecipada aos dados correspondentes recentemente recebidos, e que pode preparar especulativamente para remeter os dados supondo que eles estarão disponíveis como previsto. a unidade de interface pode monitorar os atrasos entre a resposta antecipada e a remessa dos dados, ou pelo menos a porção do atraso que pode variar. com base nos atrasos mensurados, a unidade pode modificar os atrasos previstos subsequentes.

公开(公告)号：BR112013006329A2

公开(公告)日：2016-06-21

申请号：BR112013006329

申请日：2011-08-31

Applicant: APPLE INC

Inventor： CHEN HAO ,  WADHAWAN RUCHI ,  BISWAS SUKALPA

IPC: G06F13/00

Abstract: controlador de memória de múltiplas portas com portas associadas às classes de tráfego. a presente invenção refere-se a um controlador de memória inclui múltiplas portas. cada porta pode ser dedicada a um tipo diferente de tráfego. em uma modalidade, os parâmetros de qualidade de serviço (qos) podem ser definidos para tipos de tráfego, e diferentes tipos de tráfego, e diferentes tipos de tráfego podem ter diferentes definições de parâmetro de qos. o controlador de memória pode ser configurado para operações programadas recebidas em diferentes portas com base nos parâmetros de qos. em um modalidade, o controlador de memória pode suportar a atualização dos parâmetros de qos quando operações subsequentes são recebidas e possuem parâmetros de qos mais altos, através de solicitação de banda lateral, e/ou através do envelhecimento das operações. em uma modalidade, o controlador de memória é configurado para reduzir a ênfase nos parâmetros de qos e aumentar a ênfase na otimização de largura de banda de memória à medida que as operações fluem através da tubulação de controlador de memória.

公开(公告)号：AU2011332209B2

公开(公告)日：2015-01-15

申请号：AU2011332209

申请日：2011-11-14

Applicant: APPLE INC

Inventor： MACHNICKI ERIK P ,  CHEN HAO ,  MANSINGH SANJAY

IPC: H03L7/06

Abstract: An efficient delay locked loop (DLL) training protocol during a frequency change includes an integrated circuit with a memory physical layer (PHY) unit that includes a master DLL and a slave DLL. The master DLL may delay a first reference clock by an amount, and provide a reference delay value corresponding to the delay amount. The slave DLL may delay a second reference clock by a second amount based upon a received configuration delay value. An interface unit may generate the configuration delay value based upon the reference delay value. A power management unit may provide an indication that the frequency of the second reference clock is changing. In response to receiving the indication, the interface unit may generate a new configuration delay value that corresponds to the new frequency using a predetermined scaling value and provide the new configuration delay value to the memory PHY unit.

公开(公告)号：AU2011332209A1

公开(公告)日：2013-05-09

申请号：AU2011332209

申请日：2011-11-14

Applicant: APPLE INC

Inventor： MACHNICKI ERIK P ,  CHEN HAO ,  MANSINGH SANJAY

IPC: H03L7/06

Abstract: An efficient delay locked loop (DLL) training protocol during a frequency change includes an integrated circuit with a memory physical layer (PHY) unit that includes a master DLL and a slave DLL. The master DLL may delay a first reference clock by an amount, and provide a reference delay value corresponding to the delay amount. The slave DLL may delay a second reference clock by a second amount based upon a received configuration delay value. An interface unit may generate the configuration delay value based upon the reference delay value. A power management unit may provide an indication that the frequency of the second reference clock is changing. In response to receiving the indication, the interface unit may generate a new configuration delay value that corresponds to the new frequency using a predetermined scaling value and provide the new configuration delay value to the memory PHY unit.

公开(公告)号：HK1168159A1

公开(公告)日：2012-12-21

申请号：HK12108647

申请日：2012-09-04

Applicant: APPLE INC

Inventor： BISWAS SUKALPA ,  CHEN HAO ,  WADHAWAN RUCHI

IPC: G06F20060101

Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

公开(公告)号：GB2483763B

公开(公告)日：2013-01-09

申请号：GB201115481

申请日：2011-09-08

Applicant: APPLE INC

Inventor： BISWAS SUKALPA ,  CHEN HAO ,  WADHAWAN RUCHI

IPC: G06F13/18

Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

公开(公告)号：HK1168672A1

公开(公告)日：2013-01-04

申请号：HK12109346

申请日：2012-09-21

Applicant: APPLE INC

Inventor： BISWAS SUKALPA ,  CHEN HAO ,  WADHAWAN RUCHI

IPC: G06F20060101

Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

公开(公告)号：NL2007411C2

公开(公告)日：2012-05-09

申请号：NL2007411

申请日：2011-09-14

Applicant: APPLE INC

Inventor： BISWAS SUKALPA ,  CHEN HAO ,  WADHAWAN RUCHI

IPC: G06F12/00 ,  G06F13/18

Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

公开(公告)号：NL2007411C

公开(公告)日：2012-05-09

申请号：NL2007411

申请日：2011-09-14

Applicant: APPLE INC

Inventor： BISWAS SUKALPA ,  CHEN HAO ,  WADHAWAN RUCHI

IPC: G06F12/00 ,  G06F13/18

CPC classification number: G06F13/1642 ,  G06F13/1626

公开(公告)号：MX2013002773A

公开(公告)日：2013-04-05

申请号：MX2013002773

申请日：2011-08-31

Applicant: APPLE INC

Inventor： BISWAS SUKALPA ,  CHEN HAO ,  WADHAWAN RUCHI

IPC: G06F13/00

Abstract: En una modalidad, un controlador de memoria incluye múltiples puertos. Cada puerto puede dedicarse a un diferente tipo de tráfico. En una modalidad, los parámetros de calidad de servicio (QoS) pueden definirse para los tipos de tráfico, y los diferentes tipos de tráfico pueden tener diferentes definiciones de parámetro QoS. El controlador de memoria puede configurase a operaciones programadas recibidas en los puertos diferentes basados en los parámetros QoS. En una modalidad, el controlador de memoria puede soportar la actualización de los parámetros QoS cuando las operaciones subsecuentes se reciben que tiene parámetros QoS mayores, vía la solicitud de banda lateral y/o vía el envejecimiento de las operaciones. En una modalidad, el controlador de memoria se configura para reducir el énfasis de los parámetros QoS e incrementa el énfasis en la optimización del ancho de banda de la memoria como operaciones que fluyen a través de la tubería (pipeline) del controlador de memoria.