公开(公告)号：JP2012074042A

公开(公告)日：2012-04-12

申请号：JP2011221349

申请日：2011-09-15

Applicant: Apple Inc ,  アップル インコーポレイテッド

Inventor： BISWAS SUKALPA ,  HAO CHENG ,  LUCH WADAWANG

IPC: G06F12/06

CPC classification number: G06F13/1642 ,  G06F13/1626

Abstract: PROBLEM TO BE SOLVED: To allow a memory controller to reduce emphasis on QoS parameters and to increase emphasis on memory bandwidth optimization as operations flow through a memory controller pipeline.SOLUTION: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations.

Abstract translation: 要解决的问题：允许存储器控制器减少对QoS参数的重视，并且随着操作流过存储器控制器管线而增加对存储器带宽优化的重视。 解决方案：在一个实施例中，存储器控制器包括多个端口。 每个端口可能专用于不同类型的流量。 在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。 存储器控制器可以被配置为基于QoS参数调度在不同端口上接收的操作。 在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2013058209A

公开(公告)日：2013-03-28

申请号：JP2012213127

申请日：2012-09-07

Applicant: Apple Inc ,  アップル インコーポレイテッド

Inventor： HAO CHENG ,  RAKESH L NOTANI ,  BISWAS SUKALPA

IPC: G06F12/00 ,  G11C11/407 ,  G11C11/4076

CPC classification number: G06F13/1689

Abstract: PROBLEM TO BE SOLVED: To provide techniques for determining when a data strobe signal is valid for capturing data.SOLUTION: In one embodiment, an apparatus is disclosed that includes a memory interface circuit configured to determine an initial time value for capturing data from a memory on the basis of a data strobe signal. In some embodiments, the memory interface circuit determines this initial time value by reading a known value from memory. In one embodiment, the memory interface circuit is further configured to determine an adjusted time value for capturing the data, where the memory interface circuit is configured to determine the adjusted time value by using the initial time value to sample the data strobe signal.

Abstract translation: 要解决的问题：提供用于确定数据选通信号何时对捕获数据有效的技术。 解决方案：在一个实施例中，公开了一种装置，其包括被配置为基于数据选通信号确定用于从存储器捕获数据的初始时间值的存储器接口电路。 在一些实施例中，存储器接口电路通过从存储器读取已知值来确定该初始时间值。 在一个实施例中，存储器接口电路还被配置为确定用于捕获数据的经调整的时间值，其中存储器接口电路被配置为通过使用初始时间值来采样数据选通信号来确定调整的时间值。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：BR112013006329A2

公开(公告)日：2016-06-21

申请号：BR112013006329

申请日：2011-08-31

Applicant: APPLE INC

Inventor： CHEN HAO ,  WADHAWAN RUCHI ,  BISWAS SUKALPA

IPC: G06F13/00

Abstract: controlador de memória de múltiplas portas com portas associadas às classes de tráfego. a presente invenção refere-se a um controlador de memória inclui múltiplas portas. cada porta pode ser dedicada a um tipo diferente de tráfego. em uma modalidade, os parâmetros de qualidade de serviço (qos) podem ser definidos para tipos de tráfego, e diferentes tipos de tráfego, e diferentes tipos de tráfego podem ter diferentes definições de parâmetro de qos. o controlador de memória pode ser configurado para operações programadas recebidas em diferentes portas com base nos parâmetros de qos. em um modalidade, o controlador de memória pode suportar a atualização dos parâmetros de qos quando operações subsequentes são recebidas e possuem parâmetros de qos mais altos, através de solicitação de banda lateral, e/ou através do envelhecimento das operações. em uma modalidade, o controlador de memória é configurado para reduzir a ênfase nos parâmetros de qos e aumentar a ênfase na otimização de largura de banda de memória à medida que as operações fluem através da tubulação de controlador de memória.

公开(公告)号：HK1168159A1

公开(公告)日：2012-12-21

申请号：HK12108647

申请日：2012-09-04

Applicant: APPLE INC

Inventor： BISWAS SUKALPA ,  CHEN HAO ,  WADHAWAN RUCHI

IPC: G06F20060101

Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

公开(公告)号：BR102012022563A2

公开(公告)日：2015-06-09

申请号：BR102012022563

申请日：2012-09-06

Applicant: APPLE INC

Inventor： CHEN HAO ,  NOTANI RAKESH L ,  BISWAS SUKALPA

IPC: G06F13/14

Abstract: Detecção de validação de dados dinâmica.técnicas estão descritas relativas à determinação quando um sinal de validação de dados é válido para capturar os dados. Em uma modalidade, um aparelho está descrito que inclui um circuito de interface de memória configurado para determinar um valor de tempo inicial para capturar os dados de uma memória com base em um sinal de validação de dados. Em algumas modalidades, o circuito de interface de memória pode determinar este valor de tempo inicial lendo um valor conhecido da memória. Em uma modalidade, o circuito de interface de memória está ainda configurado para determinar um valor de tempo ajustado para capturar os dados, onde o circuito de interface de memória está configurado para determinar o valor de tempo ajustado utilizando o valor de tempo inicial para amostrar o sinal de validação de dados.

公开(公告)号：AU2012216673A1

公开(公告)日：2013-03-28

申请号：AU2012216673

申请日：2012-09-05

Applicant: APPLE INC

Inventor： CHEN HOA ,  NOTANI RAKESH L ,  BISWAS SUKALPA

IPC: G11C7/22

Abstract: Techniques are disclosed relating to determining when a data strobe signal is valid for capturing data. In one embodiment, an apparatus is disclosed that includes a memory 5 interface circuit configured to determine an initial time value for capturing data from a memory based on a data strobe signal. In some embodiments, the memory interface circuit may determine this initial time value by reading a known value from memory. In one embodiment, the memory interface circuit further configured to determine an adjusted time value for capturing the data, where the memory interface circuit is 10 configured to determine the adjusted time value by using the initial time value to sample the data strobe signal. (Q Q) Cto 0 co too cn~

公开(公告)号：BR112013018123A2

公开(公告)日：2016-11-08

申请号：BR112013018123

申请日：2012-01-06

Applicant: APPLE INC

Inventor： TRIPATHI BRIJESH ,  SAUND GURJEET S ,  BISWAS SUKALPA

IPC: H04W4/00

Abstract: controle de estrutura relacionada com a qualidade do serviço (qos) a presente invenção refere-se a um ou mais circuitos de controle da estrutura que podem ser inseridos em uma estrutura de comunicação para controlar vários aspectos das comunicações pelos componentes no sistema. os circuitos de controle da estrutura podem ser incluídos na interface dos componentes para a estrutura de comunicação em algumas modalidades. em outras modalidades que incluem uma estrutura de comunicação hierárquica, os circuitos de controle da estrutura podem ser incluídos alternativa ou adicionalmente. os circuitos de controle da estrutura podem ser programáveis e, assim, proporcionar a capacidade de sintonizar a estrutura de comunicação para satisfazer metas de desempenho e/ou funcionalidade.

公开(公告)号：AU2011302452B2

公开(公告)日：2014-09-04

申请号：AU2011302452

申请日：2011-08-31

Applicant: APPLE INC

Inventor： BISWAS SUKALPA ,  CHEN HAO ,  WADHAWAN RUCHI

IPC: G06F13/00

Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

公开(公告)号：AU2012216673A8

公开(公告)日：2014-07-03

申请号：AU2012216673

申请日：2012-09-05

Applicant: APPLE INC

Inventor： CHEN HOA ,  NOTANI RAKESH L ,  BISWAS SUKALPA

IPC: G11C7/22

Abstract: Techniques are disclosed relating to determining when a data strobe signal is valid for capturing data. In one embodiment, an apparatus is disclosed that includes a memory 5 interface circuit configured to determine an initial time value for capturing data from a memory based on a data strobe signal. In some embodiments, the memory interface circuit may determine this initial time value by reading a known value from memory. In one embodiment, the memory interface circuit further configured to determine an adjusted time value for capturing the data, where the memory interface circuit is 10 configured to determine the adjusted time value by using the initial time value to sample the data strobe signal. (Q Q) Cto 0 co too cn~

公开(公告)号：AU2012216673B2

公开(公告)日：2014-02-27

申请号：AU2012216673

申请日：2012-09-05

Applicant: APPLE INC

Inventor： CHEN HOA ,  NOTANI RAKESH L ,  BISWAS SUKALPA

IPC: G11C7/22

Abstract: Techniques are disclosed relating to determining when a data strobe signal is valid for capturing data. In one embodiment, an apparatus is disclosed that includes a memory 5 interface circuit configured to determine an initial time value for capturing data from a memory based on a data strobe signal. In some embodiments, the memory interface circuit may determine this initial time value by reading a known value from memory. In one embodiment, the memory interface circuit further configured to determine an adjusted time value for capturing the data, where the memory interface circuit is 10 configured to determine the adjusted time value by using the initial time value to sample the data strobe signal. (Q Q) Cto 0 co too cn~