公开(公告)号：US20200227250A1

公开(公告)日：2020-07-16

申请号：US16827506

申请日：2020-03-23

Applicant: ASM IP Holding B.V.

Inventor： Viljami Pore ,  Werner Knaepen ,  Bert Jongbloed ,  Dieter Pierreux ,  Gido Van Der Star ,  Toshiya Suzuki

IPC: H01L21/02 ,  C23C16/04 ,  C23C16/455 ,  C23C16/50 ,  H01L21/762

Abstract: There is provided a method of filling one or more gaps by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant on a first area; introducing a second reactant to the substrate with a second dose, thereby forming no more than about one monolayer by the second reactant on a second area of the surface, wherein the first and the second areas overlap in an overlap area where the first and second reactants react and leave an initially unreacted area where the first and the second areas do not overlap; and, introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant remaining on the initially unreacted area.

公开(公告)号：US20180350623A1

公开(公告)日：2018-12-06

申请号：US15994236

申请日：2018-05-31

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Werner Knaepen ,  Bert Jongbloed

IPC: H01L21/3213 ,  H01L21/306 ,  C23F1/16

Abstract: The disclosure relates generally to the field of processing substrates, for example comprising materials such as quartz, glass or silicon. The disclosure more particular relates to providing wet etch protection layers comprising boron and carbon and etching the substrate in a hydrogen fluoride aqueous solution. One or more of the boron and carbon containing films can have a thickness of at least 5, preferably 10 and, more preferably 30 nm. The method comprises wet etching the substrate in a hydrofluoric acid solution with a hydrogen fluoride concentration of at least 10 wt. % for at least 5 minutes.

公开(公告)号：US09837281B2

公开(公告)日：2017-12-05

申请号：US15164575

申请日：2016-05-25

Applicant: ASM IP Holding B.V.

Inventor： Bert Jongbloed ,  Dieter Pierreux ,  Werner Knaepen

IPC: H01L21/308 ,  H01L21/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3115 ,  C23C16/455

CPC classification number: H01L21/3081 ,  C23C16/301 ,  C23C16/308 ,  C23C16/34 ,  C23C16/45527 ,  C23C16/45531 ,  C23C16/45561 ,  H01L21/02178 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/3115

Abstract: A process for depositing doped aluminum nitride (doped AlN) is disclosed. The process comprises subjecting a substrate to temporally separated exposures to an aluminum precursor and a nitrogen precursor to form an aluminum and nitrogen-containing compound on the substrate. The aluminum and nitrogen-containing compound is subsequently exposed to a dopant precursor to form doped AlN. The temporally separated exposures to an aluminum precursor and a nitrogen precursor, and the subsequent exposure to a dopant precursor together constitute a doped AlN deposition cycle. A plurality of doped AlN deposition cycles may be performed to deposit a doped AlN film of a desired thickness. The dopant content of the doped AlN can be tuned by performing a particular ratio of 1) separated exposures to an aluminum precursor and a nitrogen precursor, to 2) subsequent exposures to the dopant. The deposition may be performed in a batch process chamber, which may accommodate batches of 25 or more substrates. The deposition may be performed without exposure to plasma.

公开(公告)号：US20170029948A1

公开(公告)日：2017-02-02

申请号：US14811435

申请日：2015-07-28

Applicant: ASM IP Holding B.V.

Inventor： Bert Jongbloed ,  Delphine Longrie ,  Robin Roelofs ,  Lucian Jdira ,  Suvi Juhani Haukka ,  Antti Niskanen ,  Jun Kawahara ,  Yukihiro Mori

IPC: C23C16/455 ,  H01L21/285 ,  H01L21/02 ,  C23C16/52 ,  C23C16/458

CPC classification number: C23C16/45544 ,  C23C16/45527 ,  C23C16/45565 ,  C23C16/458 ,  C23C16/4583 ,  C23C16/52 ,  C23C16/54 ,  H01L21/0228 ,  H01L21/0262 ,  H01L21/28556

Abstract: In accordance with some embodiments herein, methods and apparatuses for deposition of thin films are provided. In some embodiments, a plurality of stations is provided, in which each station provides a different reactant or combination of reactants. The stations can be in gas isolation from each other, and the substrate can be contacted with different reactants at different temperatures so as to minimize or prevent undesired gas phase reactions, chemical vapor deposition (CVD) and/or atomic layer deposition (ALD) reactions between the different reactants or combinations of reactants.

Abstract translation: 根据本文的一些实施例，提供了用于沉积薄膜的方法和装置。 在一些实施例中，提供多个站，其中每个站提供不同的反应物或反应物的组合。 这些站可以彼此气体隔离，并且可以在不同的温度下将基板与不同的反应物接触，以便最小化或防止不期望的气相反应，化学气相沉积（CVD）和/或原子层沉积（ALD）反应 在不同的反应物或反应物的组合之间。

公开(公告)号：US09552979B2

公开(公告)日：2017-01-24

申请号：US13907718

申请日：2013-05-31

Applicant: ASM IP Holding B.V.

Inventor： Werner Knaepen ,  Bert Jongbloed ,  Dieter Pierreux ,  Peter Zagwijn ,  Hessel Sprey ,  Cornelius A. van der Jeugd ,  Marinus Josephus de Blank ,  Robin Roelofs ,  Qi Xie ,  Jan Willem Maes

IPC: H01L21/469 ,  H01L21/31 ,  H01L21/02 ,  C23C16/30 ,  C23C16/455 ,  C23C16/458 ,  H01L29/20

CPC classification number: H01L21/02178 ,  C23C16/303 ,  C23C16/45525 ,  C23C16/4583 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003

Abstract: A process for depositing aluminum nitride is disclosed. The process comprises providing a plurality of semiconductor substrates in a batch process chamber and depositing an aluminum nitride layer on the substrates by performing a plurality of deposition cycles without exposing the substrates to plasma during the deposition cycles. Each deposition cycle comprises flowing an aluminum precursor pulse into the batch process chamber, removing the aluminum precursor from the batch process chamber, and removing the nitrogen precursor from the batch process chamber after flowing the nitrogen precursor and before flowing another pulse of the aluminum precursor. The process chamber may be a hot wall process chamber and the deposition may occur at a deposition pressure of less than 1 Torr.

Abstract translation: 公开了一种沉积氮化铝的方法。 该方法包括在分批处理室中提供多个半导体衬底，并且通过在沉积循环期间不使衬底暴露于等离子体，通过执行多个沉积循环来在衬底上沉积氮化铝层。 每个沉积循环包括将铝前体脉冲流入分批处理室，从分批处理室中除去铝前体，以及在氮气前体流动之后并且在流过铝前体的另一个脉冲之前从分批处理室中除去氮前体。 处理室可以是热壁处理室，并且沉积可以在小于1托的沉积压力下进行。

公开(公告)号：US20160307766A1

公开(公告)日：2016-10-20

申请号：US15164575

申请日：2016-05-25

Applicant: ASM IP Holding B.V.

Inventor： Bert Jongbloed ,  Dieter Pierreux ,  Werner Knaepen

IPC: H01L21/308 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3115 ,  C23C16/455 ,  H01L21/02

CPC classification number: H01L21/3081 ,  C23C16/301 ,  C23C16/308 ,  C23C16/34 ,  C23C16/45527 ,  C23C16/45531 ,  C23C16/45561 ,  H01L21/02178 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/3115

Abstract: A process for depositing doped aluminum nitride (doped AlN) is disclosed. The process comprises subjecting a substrate to temporally separated exposures to an aluminum precursor and a nitrogen precursor to form an aluminum and nitrogen-containing compound on the substrate. The aluminum and nitrogen-containing compound is subsequently exposed to a dopant precursor to form doped AlN. The temporally separated exposures to an aluminum precursor and a nitrogen precursor, and the subsequent exposure to a dopant precursor together constitute a doped AlN deposition cycle. A plurality of doped AlN deposition cycles may be performed to deposit a doped AlN film of a desired thickness. The dopant content of the doped AlN can be tuned by performing a particular ratio of 1) separated exposures to an aluminum precursor and a nitrogen precursor, to 2) subsequent exposures to the dopant. The deposition may be performed in a batch process chamber, which may accommodate batches of 25 or more substrates. The deposition may be performed without exposure to plasma.

Abstract translation: 公开了一种沉积掺杂氮化铝（掺杂AlN）的工艺。 该方法包括使基底经历时间上分离的暴露于铝前体和氮前体，以在基底上形成含铝和氮的化合物。 随后将铝和含氮化合物暴露于掺杂剂前体以形成掺杂的AlN。 时间上分离的暴露于铝前体和氮前体，以及随后暴露于掺杂剂前体一起构成掺杂AlN沉积循环。 可以执行多个掺杂AlN沉积循环以沉积所需厚度的掺杂AlN膜。 掺杂AlN的掺杂剂含量可以通过对铝前体和氮前体进行1）分离的曝光的特定比例来调节，2）随后暴露于掺杂剂。 沉积可以在间歇处理室中进行，其可以容纳25个或更多个基底的批次。 可以在不暴露于等离子体的情况下进行沉积。

公开(公告)号：US20150303079A1

公开(公告)日：2015-10-22

申请号：US14648380

申请日：2013-12-03

Applicant: ASM IP HOLDING B.V.

Inventor： Theodorus G. M. Oosterlaken ,  Chris G. M. de Ridder ,  Bert Jongbloed

IPC: H01L21/67 ,  B23P6/00 ,  H01L21/673 ,  F27B1/20 ,  H01L21/687

CPC classification number: H01L21/67098 ,  B23P6/00 ,  F27B1/20 ,  H01L21/6719 ,  H01L21/67303 ,  H01L21/6735 ,  H01L21/67724 ,  H01L21/67775 ,  H01L21/68707

Abstract: A vertical furnace processing system for processing semiconductor substrates, comprising the following modules:—a processing module including a vertical furnace; an I/O-station module including at least one load port to which a substrate cassette is dockable; a wafer handling module configured to transfer semiconductor substrates between the processing module and a substrate cassette docked to the load port of the I/O-station module; and a gas supply module including at least one gas supply or gas supply connection for providing the vertical furnace of the processing module with process gas, wherein at least two of the said modules are mutually decouplably coupled, such that said at least two modules are decouplable from one another to facilitate servicing of the system, and in particular the vertical furnace thereof.

Abstract translation: 一种用于处理半导体衬底的立式炉处理系统，包括以下模块： - 包括立式炉的处理模块; I / O站模块，其包括至少一个负载端口，衬底盒可停靠在该负载端口上; 晶片处理模块，被配置为在所述处理模块和与所述I / O站模块的负载端口对接的基板盒之间传送半导体衬底; 以及气体供应模块，其包括至少一个气体供应或气体供应连接，用于向处理模块的立式炉提供处理气体，其中至少两个所述模块相互去耦合，使得所述至少两个模块可去耦 从而方便维修系统，特别是其立式炉。

公开(公告)号：US12077854B2

公开(公告)日：2024-09-03

申请号：US17810773

申请日：2022-07-05

Applicant: ASM IP Holding, B.V.

Inventor： Dieter Pierreux ,  Theodorus G. M. Oosterlaken ,  Herbert Terhorst ,  Lucian Jdira ,  Bert Jongbloed

IPC: C23C16/44 ,  C23C16/34 ,  C23C16/455 ,  C23C16/458 ,  C23C16/52

CPC classification number: C23C16/4405 ,  C23C16/345 ,  C23C16/455 ,  C23C16/45561 ,  C23C16/4583 ,  C23C16/52

Abstract: A chemical vapor deposition furnace for depositing silicon nitride films is disclosed. The furnace includes a process chamber elongated in a substantially vertical direction and a wafer boat for supporting a plurality of wafers in the process chamber. A process gas injector inside the process chamber is provided with vertically spaced gas injection holes to provide gas introduced at a feed end in an interior of the process gas injector to the process chamber. A valve system connected to the feed end of the process gas injector is being constructed and arranged to connect a source of a silicon precursor and a nitrogen precursor to the feed end for depositing silicon nitride layers. The valve system may connect the feed end of the process gas injector to a cleaning gas system to provide a cleaning gas to remove silicon nitride from the process gas injector and/or the process chamber.

公开(公告)号：US11990333B2

公开(公告)日：2024-05-21

申请号：US18208398

申请日：2023-06-12

Applicant: ASM IP Holding B.V.

Inventor： Viljami Pore ,  Werner Knaepen ,  Bert Jongbloed ,  Dieter Pierreux ,  Gido van Der Star ,  Toshiya Suzuki

IPC: H01L21/02 ,  C23C16/04 ,  C23C16/455 ,  C23C16/50 ,  H01L21/762

CPC classification number: H01L21/0228 ,  C23C16/045 ,  C23C16/45525 ,  C23C16/45527 ,  C23C16/45536 ,  C23C16/50 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/76224

Abstract: There is provided a method of filling one or more gaps by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant on a first area; introducing a second reactant to the substrate with a second dose, thereby forming no more than about one monolayer by the second reactant on a second area of the surface, wherein the first and the second areas overlap in an overlap area where the first and second reactants react and leave an initially unreacted area where the first and the second areas do not overlap; and, introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant remaining on the initially unreacted area.

公开(公告)号：US11887857B2

公开(公告)日：2024-01-30

申请号：US17235990

申请日：2021-04-21

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Bert Jongbloed ,  Qi Xie ,  Giuseppe Alessio Verni

IPC: H01L21/285 ,  C23C16/455 ,  C23C16/52 ,  H01L21/02 ,  C23C16/34 ,  H01L21/3205 ,  H10B43/35 ,  H01L23/535 ,  H01L29/786 ,  H01L49/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L21/28568 ,  C23C16/34 ,  C23C16/45544 ,  C23C16/52 ,  H01L21/02697 ,  H01L21/28556 ,  H01L21/32051 ,  H10B43/35 ,  H01L23/535 ,  H01L28/60 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/775 ,  H01L29/78696 ,  H10B41/27 ,  H10B43/27

Abstract: Disclosed are methods and systems for depositing layers comprising vanadium, nitrogen, and element selected from the list consisting of molybdenum, tantalum, niobium, aluminum, and silicon. The layers are deposited onto a surface of a substrate. The deposition process may be a cyclical deposition process. Exemplary structures in which the layers may be incorporated include field effect transistors, VNAND cells, metal-insulator-metal (MIM) structures, and DRAM capacitors.