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公开(公告)号：NO20020847A
公开(公告)日：2002-02-21
申请号：NO20020847
申请日：2002-02-21
Applicant: ATMEL CORP
Inventor： PATHAK SAROJ , PAYNE JAMES E , PATHAK JAGDISH
IPC: G11C16/06 , G11C7/06 , G11C7/14 , G11C16/04 , G11C16/28 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
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公开(公告)号：CA2303234A1
公开(公告)日：1999-06-03
申请号：CA2303234
申请日：1998-11-20
Applicant: ATMEL CORP
Inventor： PATHAK JAGDISH , ROSENDALE GLEN A , PATHAK SAROJ , HANGZO NIANGLAMCHING , PAYNE JAMES E
IPC: H03K17/22
Abstract: A power-on-reset circuit includes a first charging stage (162) for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means (122) for charging up a second charging stage (164). When the second charging stage reaches a first voltage level, a circuit (130) is tripped to pull the potential of the first to ground. The grounding of the first charging stage (162) is fed back to the charging means (122) which shuts off its power burning components and maintains the first voltage level at the second charging stage (164).
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公开(公告)号：NO985933D0
公开(公告)日：1998-12-17
申请号：NO985933
申请日：1998-12-17
Applicant: ATMEL CORP
Inventor： PATHAK JAGDISH
Abstract: The present invention relates to a bit line clamping scheme for non-volatile memories. The bit line voltage is maintained at a desired voltage level so as to avoid read disturb effects, while being independent of power supply variations and consuming virtually no power. The invention makes practical memory devices which are designed for both high voltage (5 volt) operation and low voltage (3.3 and 2.5 volt) operation.
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公开(公告)号：CA2261785A1
公开(公告)日：1998-11-26
申请号：CA2261785
申请日：1998-04-24
Applicant: ATMEL CORP
Inventor： PATHAK JAGDISH , PATHAK SAROJ
Abstract: A memory device includes a memory cell (102) whose data state is sensed by a sense amplifier (100). A balance amplifier (200) having the same construction as the sense amplifier is utilized to sense a balance cell (202) having the same construction as the memory cell. The balance cell is maintained in a erased (conductive) state. The balance cell is gated by the output of the sense amplifier. Such a device operates in a way to consume the same amount of power regardless of the data state of the memory cell. In one embodiment of the invention, a memory device consisting of a memory array includes a balance circuit associated with each of the sense amplifiers in the memory device. In another embodiment of the invention, a trim circuit (208) is used to adjust the conductivity of the balance circuit. This allows the balance circuit to be fine tuned during manufacture to compensate for process variations, thus allowing the balance circuit to be matched to the memory cells.
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公开(公告)号：DE60132088T2
公开(公告)日：2008-12-11
申请号：DE60132088
申请日：2001-05-14
Applicant: ATMEL CORP
Inventor： PATHAK SAROJ , PAYNE JAMES E , PATHAK JAGDISH
IPC: G11C16/06 , G11C16/28 , G11C7/06 , G11C7/14 , G11C16/04 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
Abstract: A reference cell for use in a high speed sensing circuit includes a first sub-circuit and a second sub-circuit. The first sub-circuit has a structure similar to memory cells within odd number rows of a main memory array. The second sub-circuit has a structure similar to memory cells within even numbered rows of the main memory array. If a target cell within the main memory array lies within an odd numbered row, then the first sub-circuit is selected, and if the target cell lies within an even numbered row, then second sub-circuit is selected. Both of the first and second sub-circuits include a reference transistors having its control gate broken into two parts. A first part is a poly 1 layer and is separated from the channel region by a tunneling oxide. A second part is a metal or poly 2 layer over the first part and separated from the first part by a gate oxide. A via is used to connect the first part to the second part.
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Patent Agency Ranking26.发明专利
公开(公告)号：CA2258957C
公开(公告)日：2005-06-28
申请号：CA2258957
申请日：1998-04-22
Applicant: ATMEL CORP
Inventor： PATHAK JAGDISH
Abstract: The present invention relates to a bit line clamping scheme for non-volatile memories (10). The bit line (35) voltage is maintained at a desired voltage level so as to avoid read disturb effects, while being independent of power supply variations and consuming virtually no power. The invention makes practical memory devices which are designed for both high voltage (5 volt) operation and low voltage (3.3 and 2.5 volt) operation.
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公开(公告)号：DE69825837D1
公开(公告)日：2004-09-30
申请号：DE69825837
申请日：1998-04-22
Applicant: ATMEL CORP
Inventor： PATHAK JAGDISH
Abstract: The present invention relates to a bit line clamping scheme for non-volatile memories. The bit line voltage is maintained at a desired voltage level so as to avoid read disturb effects, while being independent of power supply variations and consuming virtually no power. The invention makes practical memory devices which are designed for both high voltage (5 volt) operation and low voltage (3.3 and 2.5 volt) operation.
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公开(公告)号：AU6184201A
公开(公告)日：2002-01-02
申请号：AU6184201
申请日：2001-05-14
Applicant: ATMEL CORP
Inventor： PATHAK SAROJ , PAYNE JAMES E , PATHAK JAGDISH
IPC: G11C16/06 , G11C7/06 , G11C7/14 , G11C16/04 , G11C16/28 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
Abstract: A reference cell for use in a high speed sensing circuit includes a first sub-circuit and a second sub-circuit. The first sub-circuit has a structure similar to memory cells within odd number rows of a main memory array. The second sub-circuit has a structure similar to memory cells within even numbered rows of the main memory array. If a target cell within the main memory array lies within an odd numbered row, then the first sub-circuit is selected, and if the target cell lies within an even numbered row, then second sub-circuit is selected. Both of the first and second sub-circuits include a reference transistors having its control gate broken into two parts. A first part is a poly 1 layer and is separated from the channel region by a tunneling oxide. A second part is a metal or poly 2 layer over the first part and separated from the first part by a gate oxide. A via is used to connect the first part to the second part.
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公开(公告)号：CA2391331A1
公开(公告)日：2001-12-27
申请号：CA2391331
申请日：2001-05-14
Applicant: ATMEL CORP
Inventor： PAYNE JAMES E , PATHAK JAGDISH , PATHAK SAROJ
IPC: G11C16/06 , G11C7/06 , G11C7/14 , G11C16/04 , G11C16/28 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
Abstract: A reference cell (47) for use in a high speed sensing circuit includes a fir st sub-circuit (73) and a second sub-circuit (71). The first sub-circuit (73) h as a structure similar to memory cells within odd number rows of a main memory array. The second sub-circuit (71) has a structure similar to memory cells within even numbered rows of the main memory array. If a target cell within the main memory array lies within an odd numbered row, then the first sub- circuit is selected, and if the target cell lies within an even numbered row , then second sub-circuit is selected. Both of the first and second sub-circui ts include a reference transistor (85, 75) having its control gate (99, 91) broken into two parts. A first part is a poly 1 layer and is separated from the channel region by a tunneling oxide. A second part is a metal or poly 2 layer over the first part and separated from the first part by a gate oxide. A via (101, 95) is used to connect the first part to the second part.
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公开(公告)号：NO20002194A
公开(公告)日：2000-07-24
申请号：NO20002194
申请日：2000-04-27
Applicant: ATMEL CORP
Inventor： PATHAK JAGDISH , PATHAK SAROJ , ROSENDALE GLEN A , PAYNE JAMES E , HANGZO NIANGLAMCHING
CPC classification number: H03K17/223
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