公开(公告)号：US20240241561A1

公开(公告)日：2024-07-18

申请号：US18622481

申请日：2024-03-29

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Karl D. Wulcan ,  Tal Kuzi ,  Inder M. Sodhi ,  Achmed R. Zahir ,  Ilya Granovsky ,  Nir Leshem ,  Lior Zimet

IPC: G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3293 ,  G06F1/3296

CPC classification number: G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3293 ,  G06F1/3296

Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Trigger logic circuits and rate control circuits may be implemented in combination with a power management circuit to control power provided to components of the integrated circuits. Power may be controlled based on receiving trigger signals from a power management unit. The power management circuit may implement power budgets for various components in the integrated circuits.

公开(公告)号：US11836026B1

公开(公告)日：2023-12-05

申请号：US17673870

申请日：2022-02-17

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Ami Schwartzman ,  Lior Zimet

IPC: G06F1/28

CPC classification number: G06F1/28

Abstract: A system includes multiple hardware circuits and protection circuitry. The multiple hardware circuits are coupled to respective power domains having respective sets of domain-specific power settings. The protection circuitry is configured to monitor requests in which one or more of the hardware circuits request transitions between the domain-specific power settings, to determine, from among multiple system-level combinations of the domain-specific power settings, a subset of system-level combinations that could potentially be traversed in performing the requested transitions, and to initiate a responsive action upon detecting that any of the system-level combinations in the subset is specified as invalid.

公开(公告)号：US11822411B2

公开(公告)日：2023-11-21

申请号：US17313837

申请日：2021-05-06

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Karl Daniel Wulcan ,  Lital Levy-Rubin ,  Tal Kuzi

IPC: G06F1/3206 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F1/3206 ,  G06F11/3003 ,  G06F11/3062 ,  G06F11/3495

Abstract: Systems, apparatuses, and methods for implementing telemetry push aggregation techniques are described. A computing system includes one or more input/output (I/O) agents interposed between functional units and a communication fabric. A given I/O agent receives a set of aggregation rules from a power management unit. The I/O agent monitors traffic from the functional units, and the I/O agent generates telemetry data from the traffic data based on the set of aggregation rules. The telemetry data is used by the power management unit to make adjustments to one or more power settings.

公开(公告)号：US20230280772A1

公开(公告)日：2023-09-07

申请号：US18314872

申请日：2023-05-10

Applicant: APPLE INC.

Inventor： Doron Rajwan ,  Craig S Forbell ,  Jamie L. Langlinais

IPC: G05F1/46

CPC classification number: G05F1/46

Abstract: An apparatus includes hardware circuits, a front-end power supply, voltage regulators, and control circuitry. The front-end power supply generates electrical power for the hardware circuits. The front-end power supply includes power stages that generate portions of electrical power and are activated and deactivated independently. The voltage regulators are connected to an output of the front-end power supply and provide adjustable operating voltages to the hardware circuits. The control circuitry controls the voltage regulators to supply the adjustable operating voltages responsively to requests from the hardware circuits, compares the adjustable operating voltages to settings that are specified as safe for provisioning by a predefined partial number of the power stages of the front-end power supply, and adaptively activates and deactivates the power stages, including ensuring that a number of active power stages is set to the predefined partial number only while the operating voltages match the safe settings.

公开(公告)号：US11709512B2

公开(公告)日：2023-07-25

申请号：US17572664

申请日：2022-01-11

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Craig S Forbell ,  Jamie L Langlinais

IPC: G05F1/62 ,  G05F1/46

CPC classification number: G05F1/46

Abstract: An apparatus includes hardware circuits, a front-end power supply, voltage regulators, and control circuitry. The front-end power supply generates electrical power for the hardware circuits. The front-end power supply includes power stages that generate portions of electrical power and are activated and deactivated independently. The voltage regulators are connected to an output of the front-end power supply and provide adjustable operating voltages to the hardware circuits. The control circuitry controls the voltage regulators to supply the adjustable operating voltages responsively to requests from the hardware circuits, compares the adjustable operating voltages to settings that are specified as safe for provisioning by a predefined partial number of the power stages of the front-end power supply, and adaptively activates and deactivates the power stages, including ensuring that a number of active power stages is set to the predefined partial number only while the operating voltages match the safe settings.

公开(公告)号：US20230063331A1

公开(公告)日：2023-03-02

申请号：US17676668

申请日：2022-02-21

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Doron Rajwan ,  Tal Kuzi ,  Nir Leshem ,  Lior Zimet

IPC: G06F1/324 ,  G06F1/3206

Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Certain techniques include the implementation of rate control circuits to control a clock rate for circuits associated with a communication fabric in an integrated circuit. The clock rate may be reduced based trigger signals received from power delivery trigger circuits coupled to the integrated circuit and voltage regulators providing power to the integrated circuit. Additional techniques may include the use of rate limiter circuits in a memory pipeline.

公开(公告)号：US20230031415A1

公开(公告)日：2023-02-02

申请号：US17387376

申请日：2021-07-28

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Tal Kuzi ,  Keith Cox ,  Yizhang Yang

IPC: G06F1/20 ,  G06F1/08 ,  G06F11/30

Abstract: A temperature control apparatus is disclosed. An integrated circuit (IC) includes a plurality of temperature sensors, a first thermal control loop, and a second thermal control loop. The first thermal control loop is configured to control temperature of the IC by reducing a frequency of a clock signal provided to the IC in response to a temperature at one of the plurality of temperature sensors reaching a first temperature threshold. The second thermal control loop is configured to control temperature of the IC by dithering the clock signal provided to the IC in response to a temperature at one of the plurality of temperature sensors reaching a second temperature threshold that is greater than the first temperature threshold.

公开(公告)号：US20210320826A1

公开(公告)日：2021-10-14

申请号：US17164482

申请日：2021-02-01

Applicant: Apple Inc.

Inventor： Luca O. Iuliano ,  Doron Rajwan ,  Ali Rabbani Rankouhi

IPC: H04L25/02 ,  H04L1/00 ,  H04L25/49

Abstract: An apparatus includes a decoding circuit, and a communication bus that is configured to transfer a particular data payload and a control signal that indicates whether the particular data payload includes a mask value. The mask value is indicative of enabled and non-enabled data words in the particular data payload. The decoding circuit is configured to receive, from an encoding circuit via the communication bus, the particular data payload and the control signal. In response to a determination that the control signal indicates that the particular data payload does not include the mask value, the decoding circuit is configured to use a default value for the mask value, and to create an uncompressed data payload from the particular data payload using the default value, wherein the default value causes the decoding circuit to maintain positions of data words between the particular data payload and the uncompressed data payload.

公开(公告)号：US12197265B2

公开(公告)日：2025-01-14

申请号：US18510525

申请日：2023-11-15

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Karl Daniel Wulcan ,  Lital Levy-Rubin ,  Tal Kuzi

IPC: G06F1/3206 ,  G06F11/30 ,  G06F11/34

Abstract: Systems, apparatuses, and methods for implementing telemetry push aggregation techniques are described. A computing system includes one or more input/output (I/O) agents interposed between functional units and a communication fabric. A given I/O agent receives a set of aggregation rules from a power management unit. The I/O agent monitors traffic from the functional units, and the I/O agent generates telemetry data from the traffic data based on the set of aggregation rules. The telemetry data is used by the power management unit to make adjustments to one or more power settings.

公开(公告)号：US20240411716A1

公开(公告)日：2024-12-12

申请号：US18811861

申请日：2024-08-22

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Lior Zimet ,  Sagi Lahav

IPC: G06F15/78 ,  G06F13/40

Abstract: An electronic device includes circuitry and a plurality of ports. The plurality of ports includes an input port and an output port, configured to communicate data units with one or more other devices across a fabric of a System on a Chip (SoC), the data units include N data bits, N being an integer larger than 1. The circuitry is configured to receive an input data unit via the input port, to make a random decision of whether to invert the N data bits in the input data unit, to produce an output data unit by retaining or inverting the N data bits of the input data unit based on the random decision, and to send the output data unit via the output port.