公开(公告)号：GB2215878A

公开(公告)日：1989-09-27

申请号：GB8806852

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT ,  KENT OSMAN

IPC: G06F9/38 ,  G06F15/78

Abstract: A multiprocessor numeric processing subsystem, wherein the interface to the arithmetic hardware 130 is so constrained that a variety of integrated circuits can be readily substituted. To compensate for the different pin-out and routing requirements of different chips, exchangeable subboards are preferably used to mount the arithmetic chips. To achieve this chip-independence without sacrificing speed, an extremely flexible and highly multiported register file is preferably used at the interface from a cache memory 140 to the numeric processing subsystem. To acheive algorithm flexibility, parallel writes from data cache memory to the control storage of the numeric processing subsystem are preferably used.

公开(公告)号：GB2215875A

公开(公告)日：1989-09-27

申请号：GB8806849

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/38 ,  G06F15/78

Abstract: A numeric processing subsystem, where at least three processors concurretly run separate processes. One of these processors is a data transfer processor, 180, which operates concurrently with a control processor, 110, for controlling the external interface, 150-180, and a third processor, 130, executes floating point operations. The floating point processor operates concurrently with and asynchronously of the control processor and the data transfer processor, and executes instructions from a control store via a high speed cache memory 140 linked to the floating point processor by a high-bandwidth bus, 144. The control processor contains microcode instructions of which some fields are stored in a first control store integrated with the arithmetic logic and other fields are stored in a second control store which controls access to the FP processor.