公开(公告)号：GB2217057A

公开(公告)日：1989-10-18

申请号：GB8806857

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/22 ,  G06F9/26

Abstract: A new architecture for microcoded computer systems. The valuable capability of multiway branching is made more flexible, and significant constraints on it are removed, by using the relative addressing capability of a sequencer to remove address boundary constraints. A shift control input permits the increment between the destination addresses to be varied. Logic 3010, 3020 receives the shift control input and tested (status) bits to provide an offset for use by sequencer 310 in forming the address of the next instruction to be executed.

公开(公告)号：GB2217062A

公开(公告)日：1989-10-18

申请号：GB8806862

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F1/08 ,  G06F15/80

Abstract: A numeric processing computer system, wherein a "smart" clock generator is built in a different technology than the arithmetic calculation units and sequencing logic. The clock generator can provide variable-length clock signals to the arithmetic units, the semiconductor technology of which has a minimum gate delay greater than three times (at comparable dimensions) that of the integrated circuit of the clock generator. The sequencing logic technology has a minimum gate delay greater than four times (at comparable dimensions) that of the clock generator.

公开(公告)号：GB2215884A

公开(公告)日：1989-09-27

申请号：GB8806869

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/24

Abstract: A multiprocessor system includes a numeric processing module 130 connected to a cache memory 140 by a very wide cache bus 144. The numeric processing module interfaces to the cache bus in a way that permits microinstructions to be transferred in parallel over the cache bus. This permits the large bandwidth of the cache bus to be exploited for microcode overlays. This system even makes dynamic paging of microcode practical in some applications.

公开(公告)号：GB2217060A

公开(公告)日：1989-10-18

申请号：GB8806860

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT ,  AHISHALILAR YAVUZ

IPC: G06F9/38 ,  G06F15/78

Abstract: A processing subsystem which includes at least four processors, all concurrently operable, including a control processor 110, a data transfer processor 120, and at least two general-purpose numeric processors 130, connected in parallel on a very wide cache bus 144. The numeric processors are commanded by the control processor to execute respective sequences of instructions, but operate asynchronously with the control processor.

公开(公告)号：GB2217056A

公开(公告)日：1989-10-18

申请号：GB8806856

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/38 ,  G06F15/78

Abstract: A dual port memory 430 is used, partitioned in software so that the top half of the memory is allocated to the control processor, (110) and the bottom half to the floating point is processor (130). This allocation is switched when both processors set respective flag bits indicating that they are ready to switch. On accesses to this memory, additional bits tag the access as "physical," "logical," or "preview". A physical access is interpreted as a literal address within the full memory, and the double buffering is ignored. A logical access is supplemented by an additional address bit, determined by the double buffering switch state. A preview access is used for read access only, and goes to the opposite bank of memory from that which would be accessed in a logical access. The use of preview can be particularly advantageous in avoiding data flow inefficiencies at synchronization points in pipelined algorithms. Preferably double buffering is used in a register file at the interface between the numeric processor and the large data cache memory (140) in the multiprocessor system. The partitioning of the register file avoids data collisions in the cache memory.

公开(公告)号：GB2215883A

公开(公告)日：1989-09-27

申请号：GB8806868

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/24 ,  G06F12/08 ,  G06F12/0886

Abstract: A processing sub-system of the system includes concurrently asynchronously operable processors including a numerical processor, 130, and a cable memory 140 having a storage capacity of at least one megabyte and which is more than sixty-four bits wide. The interface between processor and cache includes a set of multiple registers in parallel, each one word wide. The registers provide parallel interface to cache and serial to a respective processor. Each register connects to a respective processor. Each register connects to a respective enable line. The architective allow processors to conduct parallel read write operations to cache. The separate enable line allow selectable masking of parallel write operations so that read-modify-write cycles are not necessary.

公开(公告)号：GB2215882A

公开(公告)日：1989-09-27

申请号：GB8806867

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/22

Abstract: A multiprocessor system, where a control processor 110 controls all data transfers to and from a numeric processing module 130, and the control processor executes essentially the same microcode for essentially all operations (by the numeric processor) of a given formal type. For example, vector adds, vector subtracts, and vector multiplies are all didactic operations, i.e. they map two vectors onto a third vector, and have common control processor microcode although the numeric processor microcode varies according to the operation performed.

公开(公告)号：GB2215879A

公开(公告)日：1989-09-27

申请号：GB8806853

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/22

Abstract: A numeric processing portion, of a multiprocessor subsystem, which uses compacted microcode. A bypass register is used to permit selected bits in microcode instruction fields to be replaced, when the instruction is called from writable control storage, 220 by other bits passed down from a higher-level processor. Instruction decode logic 260 is connected to receive and decode microcoded instructions called by program counter logic from the program memory. The decode logic combines an operation specifier read from an instruction register with a microinstruction called from the program memory to provide a complete microinstruction for execution.

公开(公告)号：GB2215877A

公开(公告)日：1989-09-27

申请号：GB8806851

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/38 ,  G06F15/78

Abstract: A processing subsystem which includes one or more numeric processors, 130, and also at least one application-customized processor. The application-customized processor is particular adapted for some particular class of operations, such as discrete Fourier transform operations, and the numeric processor provides acceptably high speed on the general range of numeric computations. A control processor, 110 runs concurrently to the other processors, and can perform many tasks invisibly to them (such as address calculation and data transfer). Preferably a separate data transfer processor 120 is used, which handles external interface needs, and which also runs concurrently in background to the numeric and application-specific processors.

公开(公告)号：GB2223609A

公开(公告)日：1990-04-11

申请号：GB8806865

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/38 ,  G06F15/78

Abstract: A multiprocessor numeric processing system, including one or more numeric processing modules. A modular interface permits multiple numeric processing modules 130 (of different types if desired) to be connected in parallel. A high- bandwidth bus 144 connects the numeric processing module(s) to a data cache memory 140 and at least one data cache memory expansion module 4310. A control processor 110 controls data transfers into and out of each of the numeric processing modules. Control of these data transfers is accomplished by an extension of the control processor's microcode. Extensions of the control processor's writable control storage are located on each of the numeric processing modules. Each of the extensions includes ifs own decode logic, and stores its own executable microinstructions.