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公开(公告)号：TW201727203A
公开(公告)日：2017-08-01
申请号：TW105129701
申请日：2016-09-13
Applicant: 標竿科技公司 , BENCHMARK TECHNOLOGIES, INC.
Inventor： 屠 宇強 , TU, YUQIANG , 萊諾德 派翠克 , REYNOLDS, PATRICK
CPC classification number: G01J4/04 , G03F1/44 , G03F7/70566 , G03F7/70641
Abstract: 本發明提供一種用於特徵化和一光源之電磁光束相關聯的光束參數的方法及設備。該光源會經由以一基板之聚焦平面為基準的一組焦距來曝光一相位移標靶。於該組焦距的每一個焦距處量測定位值，並且利用定位值來決定以焦距為函數的一或更多個定位斜率。比較該些定位斜率及基線定位斜率，以便特徵化討論中的光束參數的目前相對狀態。可以依此方式貝特徵化的光束參數包含偏振度以及以一初始偏振方向為基準的偏振旋轉。本發明還說明有利於光束特徵化的相位移測試圖樣。
Abstract in simplified Chinese: 本发明提供一种用于特征化和一光源之电磁光束相关联的光束参数的方法及设备。该光源会经由以一基板之聚焦平面为基准的一组焦距来曝光一相位移标靶。于该组焦距的每一个焦距处量测定位值，并且利用定位值来决定以焦距为函数的一或更多个定位斜率。比较该些定位斜率及基线定位斜率，以便特征化讨论中的光束参数的目前相对状态。可以依此方式贝特征化的光束参数包含偏振度以及以一初始偏振方向为基准的偏振旋转。本发明还说明有利于光束特征化的相位移测试图样。
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公开(公告)号：GB2217062A
公开(公告)日：1989-10-18
申请号：GB8806862
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： BALDWIN DAVID ROBERT
Abstract: A numeric processing computer system, wherein a "smart" clock generator is built in a different technology than the arithmetic calculation units and sequencing logic. The clock generator can provide variable-length clock signals to the arithmetic units, the semiconductor technology of which has a minimum gate delay greater than three times (at comparable dimensions) that of the integrated circuit of the clock generator. The sequencing logic technology has a minimum gate delay greater than four times (at comparable dimensions) that of the clock generator.
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公开(公告)号：GB2215956A
公开(公告)日：1989-09-27
申请号：GB8806874
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： TREVETT NEIL FRANCIS , WILSON MALCOLM ERIC
Abstract: A system and method for performing image clipping is disclosed. The system includes a RAM based clipper which can clip image data automatically, to arbitrary shapes, without the use of manipulative software. The preferred embodiment of the present system includes image clipping logic in the form of an Arbitrary Shape Clipper (ASC) 112. The ASC reduces image clipping time and allows for complex window management. In its preferred embodiment, the ASC includes a random access memory (RAM) which is used to store a bit mapped pattern defined by the shape of the non-obscured portion of a displayed window. The ASC uses this pattern to automatically clip (in gate 114) an image to the contours of the non- obscured portion of the window by write disabling the screen refresh memory 102 for addresses corresponding to any obscured portions of the active window. Advantageously, the use of a RAM stored, bit mapped pattern allows an image to be clipped, almost instantaneously, to even arbitrary and complex contours.
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公开(公告)号：GB2215954A
公开(公告)日：1989-09-27
申请号：GB8806872
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： TREVETT NEIL FRANCIS , WILSON MALCOLM ERIC
Abstract: A system and method for performing window management using hardware is disclosed. The system preferably includes several subsystems which can function synergisticly to accomplish fast and efficient window management. In one embodiment the system makes use of simultaneous accessable on and off screen memories 102, 104 respectively which have the ability to perform inter-memory image data translation and high speed copy operations. Offsetting the addressing (110) of the off-screen memory relative to the screen refresh memory furthers the manipulation ability. In another embodiment, a RAM based arbitary shape clipper 112 is provided so that image data may be clipped automatically, to any arbitrary shape, without the use of manipulative software. The system can also make use of an I/O bus converter so that windows may be displayed directly from an input device such as a camera.
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公开(公告)号：GB2215953A
公开(公告)日：1989-09-27
申请号：GB8806848
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： TREVETT NEIL FRANCIS , WILSON MALCOLM ERIC
IPC: G06T1/20
Abstract: The present invention is a system architecture and methods of operation which reaps all the advantages of patch access processing while allowing many important types of image manipulation to be performed to the granularity and addressability of a single pixel. It goes beyond conventional concepts of the limits of pixel granularity by manipulating pixel data across and within bit planes in a manner which enables bit positions to be exchanged within the same pixel and/or swapped between different pixels.
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Patent Agency Ranking
公开(公告)号：GB2215950A
公开(公告)日：1989-09-27
申请号：GB8806841
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： TREVETT NEIL FRANCIS , WILSON MALCOLM ERIC
IPC: G06T1/20
Abstract: A system and method for performing raster operations in a patch access environment utilizes two or more source patches to produce an Y shifted destination patch. Even though the present invention operates in a patch access environment, it can form a destination patch by merging groups of pixels not residing within the same patch boundaries. The Y shifting and merging used to form the Y shifted destination patch can be done on a patch plane basis or on a patch basis. A line of Y shifted patches is stored in a memory. A second contiguous line of Y shifted patches is also stored in the memory. The stored lines are merged and Y shifted output patches can be read out of the memory in a page mode fashion. Boolean or arithmetic operations can be performed between the Y shifted patch and pre-existing data within a destination patch area so as to produce the Y shifted destination patch.
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公开(公告)号：GB2215948A
公开(公告)日：1989-09-27
申请号：GB8806837
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： TREVETT NEIL FRANCIS , WILSON MALCOLM ERIC
IPC: G06T1/20
Abstract: A system and method for performing raster operations in a patch access environment utilizes two or more source patches to produce an XY shifted destination patch. Even though the present invention operates in a patch access environment, it can form a destination patch by merging groups of pixels not residing within the same patch boundaries. The shifting and merging used to form the XY shifted destination patch can be done on a patch plane basis or on a patch basis. The X shifting and merging effectively combines preselected contiguous columns of contigous patches. The X shifted patches are then shifted in the Y direction to produce XY shifted patches. A line of the XY shifted patches is stored in a memory. A second, contiguous line of XY shifted patches is also stored in the memory. The stored lines of XY shifted patches are merged and merged XY shifted patches can be read out of the memory in a page mode fashion. Boolean or arithmetic operations can be performed between the merged XY shifted patch and pre-existing data within a destination patch area so as to produce the XY shifted destination patch.
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公开(公告)号：GB2215936A
公开(公告)日：1989-09-27
申请号：GB8806878
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： TREVETT NEIL FRANCIS , WILSON MALCOLM ERIC
Abstract: A method of producing a real time video window on a video monitor having a first frame rate eg 60 HZ non-interlaced from a source e.g. a T.V. camera having a second frame rate e.g. 25-30 HZ interlaced other than that of the video monitor comprising the steps of: providing image data from the video source, at the second frame rate; storing the image data at the second frame rate, in an off screen non displayable memory 104 at addresses where the image data is to appear in a screen refresh memory 102; block copying the image data from the off screen memory 104 to the screen refresh memory 102 by providing a single source of address data (106, 108, 110); and providing the image data to the video monitor at the first frame rate.
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公开(公告)号：GB2215884A
公开(公告)日：1989-09-27
申请号：GB8806869
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： BALDWIN DAVID ROBERT
IPC: G06F9/24
Abstract: A multiprocessor system includes a numeric processing module 130 connected to a cache memory 140 by a very wide cache bus 144. The numeric processing module interfaces to the cache bus in a way that permits microinstructions to be transferred in parallel over the cache bus. This permits the large bandwidth of the cache bus to be exploited for microcode overlays. This system even makes dynamic paging of microcode practical in some applications.
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公开(公告)号：GB8806881D0
公开(公告)日：1988-04-27
申请号：GB8806881
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Abstract: A system and method merges two or more analog video signals (Channels 1,2) under control of a third analog video signal 154. A standard video output from one processor's video signal digital to analog converter (DAC) is used as the control signal for the merging of two or more other video signals. This enables the video outputs of even highly diverse processing schemes to be easily merged. In its preferred embodiment, the system includes analog switching circuitry (140-142) which is used to mix the video outputs from two or more different systems. The system also includes circuitry (110) which converts the standard video output from a third processor into a large swing TTL signal which is used to control the analog switch.
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