公开(公告)号：WO1993019418A1

公开(公告)日：1993-09-30

申请号：PCT/US1993002241

申请日：1993-03-11

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  BEHRENS, Richard, T. ,  ANDERSON, Kent, D. ,  GLOVER, Neal

IPC: G06F11/10

CPC classification number: G11B20/1426 ,  G11B20/1833 ,  H03M13/41 ,  H03M13/4107 ,  H04L25/4906 ,  H04L25/497

Abstract: In a typical Viterbi demodulator implemented using the add, compare, select (ACS) method, each state in the expected sample sequence model is associated with a hardware module to perform the functions of adding new branch error metrics to path error metrics, comparing path error metrics, and selecting the path having the lowest path error metric. An ACS module may have two or more sequence-model states dynamically associated with it, such that at some times one sequence-model state is associated with it and at other times another sequence-model state is associated with it. This reduces the number of ACS modules required and also reduces the size/complexity of the demodulator's path memories which must store one path for each ACS module. Groups of sequence-model states may be chosen to share an ACS module without significant loss in performance as compared to the original, unreduced Viterbi demodulator.

Abstract translation: 在使用加法，比较，选择（ACS）方法实现的典型维特比解调器中，预期采样序列模型中的每个状态与硬件模块相关联，以执行向路径误差度量添加新的分支误差度量的功能，比较路径误差 度量，并选择具有最低路径错误度量的路径。 ACS模块可以具有与其动态相关联的两个或更多个序列模型状态，使得在某些时候一个序列模型状态与其相关联，并且在其他时间，另一个序列模型状态与其相关联。 这减少了所需的ACS模块的数量，并且还降低了解调器的路径存储器的大小/复杂性，这些存储器必须存储每个ACS模块的一个路径。 与原始的未导通的维特比解调器相比，可以选择一组序列模型状态来共享ACS模块，而没有显着的性能损失。

公开(公告)号：WO1999009491A1

公开(公告)日：1999-02-25

申请号：PCT/US1997019332

申请日：1997-10-23

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  GONG, Xue-Mei

IPC: G06F17/18

CPC classification number: G06F17/18 ,  H03M3/332 ,  H03M3/35 ,  H03M3/43 ,  H03M3/458 ,  H03M3/50

Abstract: A delta-sigma analog/digital converter is provided for operating in the analog domain to generate a digital value that is to be processed by a digital signal processor (DSP) (26) to provide on the output a digital output. Each data node in each processing element in the DSP (26) is mirrored by the way of a corresponding data node in the mirror circuit (36). This results in the addition of noise via a noise adder (28) such that each data node in the main portion of the DSP (26) that can draw current from the power supply during a transition will have a corresponding complement node in the mirror circuit (36). Each data node in the mirror circuit will add noise via a transition drawing current from the power supply whenever the transition does not occur at the corresponding data node in the main portion of the DSP (26). Therefore, di/dt noise will be added for each cycle, regardless of the data pattern. This is effected by insuring that, for each data cycle, each data node undergoes a positive and a negative transition. By using a return-to-zero data stream, i.e., inserting a zero in each cycle at each data node, a positive transition and a negative transition can be during each data cycle.

Abstract translation: 提供了一个Δ-Σ模拟/数字转换器，用于在模拟域中操作以产生要由数字信号处理器（DSP）（26）处理的数字值，以在输出端提供数字输出。 DSP（26）中的每个处理元件中的每个数据节点通过镜像电路（36）中对应的数据节点的方式进行镜像。 这导致通过噪声加法器（28）增加噪声，使得在转换期间能够从电源抽取电流的DSP（26）的主要部分中的每个数据节点将在镜像电路中具有相应的补码节点 （36）。 只要在DSP（26）的主要部分中的相应数据节点处不发生转换，镜像电路中的每个数据节点将通过来自电源的转移绘制电流来增加噪声。 因此，无论数据模式如何，都会为每个周期添加di / dt噪声。 这通过确保对于每个数据周期，每个数据节点经历正和负转换来实现。 通过使用归零数据流，即在每个数据节点处在每个周期中插入零，可以在每个数据周期期间进行正转移和负转移。

公开(公告)号：WO1998029859A3

公开(公告)日：1998-07-09

申请号：PCT/US1997023908

申请日：1997-12-24

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  WILDE, Daniel

IPC: G09G05/02

公开(公告)号：WO1998027499A1

公开(公告)日：1998-06-25

申请号：PCT/US1997023981

申请日：1997-12-19

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  LEE, Kuochun ,  CHEN, Tsung-Chen ,  WANG, Fong-Jim

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5045

Abstract: A method and system to efficiently incorporate engineering change order (ECO) modifications into an integrated circuit layout having configurable gate array cells is provided. In generating the original integrated circuit layout, extra gate array cells are inserted into the layout. These gate array cells can be reconfigured to modify their functionality according to changes specified by the ECO. A new netlist with a description of the required modifications is generated and provided to a place-and-route CAD tool to create a new layout of the integrated circuit.

Abstract translation: 提供了一种将工程变更顺序（ECO）修改有效地结合到具有可配置门阵列单元的集成电路布局中的方法和系统。 在生成原始集成电路布局时，将额外的门阵列单元插入到布局中。 这些门阵列单元可以根据ECO指定的更改进行重新配置以修改其功能。 生成一个包含所需修改描述的新网表，并将其提供给位置和路径CAD工具，以创建集成电路的新布局。

公开(公告)号：WO1998025270A1

公开(公告)日：1998-06-11

申请号：PCT/US1997022002

申请日：1997-12-03

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  RAO, G., R., Mohan ,  PATEL, Kirit, B.

IPC: G11C07/06

CPC classification number: G11C7/06 ,  G11C11/4091

Abstract: A step generator (800) including at least one gate (805) and a voltage divider (806) coupled to an output of gate (805). The selected node of voltage divider (806) provides an output VOUT of generator (800). Circuitry (801) presents a signal to an input of gate (805) to initiate current flow through voltage divider (806).

Abstract translation: 包括耦合到门（805）的输出的至少一个门（805）和分压器（806）的步进发生器（800）。 分压器（806）的选定节点提供发电机（800）的输出VOUT。 电路（801）向门（805）的输入提供信号以启动通过分压器（806）的电流。

公开(公告)号：WO1998014015A3

公开(公告)日：1998-04-02

申请号：PCT/US1997017165

申请日：1997-09-24

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  LEGER, Geary ,  CARPENTER, Peter ,  TANG, Tong

IPC: H04L29/06

公开(公告)号：WO1996033498A1

公开(公告)日：1996-10-24

申请号：PCT/US1996005523

申请日：1996-04-19

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  SHARMA, Sudhir ,  RUNAS, Michael, E. ,  NALLY, Robert, M.

IPC: G11C07/00

CPC classification number: G11C7/00 ,  G11C7/1006

Abstract: A memory system (104) is provided which includes an array (200) of memory cells arranged in rows and columns. Circuitry (207, 208, 209, 210) is also provided for selectively performing logic operations on a bit of data stored in a selected memory cell using a bit of received modifying data. Circuitry (207, 208, 209, 210) for performing logic operations is operable during an AND operation to write the bit of modifying data into the selected memory cell when the bit of modifying data is a logic zero and maintains an existing bit stored in the selected cell when the bit of modifying data is a logic one.

Abstract translation: 提供了一种存储器系统（104），其包括以行和列布置的存储器单元的阵列（200）。 还提供电路（207,208,209,210），用于使用接收到的修改数据的位来选择性地对存储在所选择的存储器单元中的数据的位进行逻辑运算。 用于执行逻辑操作的电路（207,208,209,210）在AND操作期间可操作以在修改数据的位为逻辑零时将修改数据的位写入所选择的存储单元中，并维持存储在所述存储单元 当修改数据的位是逻辑1时，选择的单元格。

公开(公告)号：WO1996030949A1

公开(公告)日：1996-10-03

申请号：PCT/US1996004331

申请日：1996-03-28

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  KESHTOBD, Parviz

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate (42) and the bit line (46) during programming. The erase operation is done by tunneling of electrons from the sharp tip of the floating gate (42) to the control gate (38) through a tunneling insulator layer (50). The floating gate (42) is formed adjacent a sidewall of a bit layer (46) which is preferably formed of tungsten or tungsten alloy. The cell is adapted so that the source (32) for each cell within the array is the source of an adjacent cell and the drain (34) is the drain to another adjacent cell. A method of manufacturing the above EPROM cell is also described.

Abstract translation: 闪存EPROM单元通过在编程期间在浮动栅极（42）和位线（46）之间提供垂直耦合而具有减小的单元尺寸。 擦除操作是通过将隧道绝缘层（50）从电荷从浮栅（42）的尖端引到控制栅（38）的方式进行的。 浮动栅极（42）形成在位于优选由钨或钨合金形成的位层（46）的侧壁附近。 单元适于使得阵列内的每个单元的源极（32）是相邻单元的源极，而漏极（34）是到另一相邻单元的漏极。 还描述了制造上述EPROM单元的方法。

公开(公告)号：WO1996010254A3

公开(公告)日：1996-04-04

申请号：PCT/US1995012386

申请日：1995-09-26

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  BEHRENS, Richard, T. ,  DUDLEY, Trent ,  BLISS, William, G.

IPC: G11B20/10

公开(公告)号：WO1995030308A1

公开(公告)日：1995-11-09

申请号：PCT/US1995005287

申请日：1995-04-28

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  EGLIT, Alexander ,  BINDLISH, Rakesh, Kumar ,  BRIL, Vlad

IPC: H04N07/26

CPC classification number: H04N21/4143 ,  G09G5/395 ,  G09G5/42 ,  H04N19/00 ,  H04N19/98

Abstract: Motion video may be imported into a personal or portable computer through an I/O port having a limited data bandwidth, such as a PCMCIA interface. Motion video data is compressed by sub-sampling both luminance and chrominance difference data for different sized groups of pixels. The compression apparatus may be formed on a PCMCIA card which interfaces with a personal or portable computer. Motion video data, compressed by as much as 5:1 or 6:1, is transferred through the PCMCIA card to a host computer. The host computer may serialize the compressed data and store the data in serialized compressed format in a video memory of a video controller. The video controller is provided with decompression circuitry to decompress the motion video data into luminance and chrominance difference data. The luminance and chrominance difference data is converted into RGB data and displayed in a video display.

Abstract translation: 运动视频可以通过具有有限数据带宽的I / O端口（例如PCMCIA接口）导入个人或便携式计算机。 运动视频数据通过对不同大小的像素组的亮度和色差差分数据进行二次采样而被压缩。 压缩装置可以形成在与个人或便携式计算机接口的PCMCIA卡上。 压缩多达5：1或6：1的运动视频数据通过PCMCIA卡传输到主机。 主机可以串行化压缩数据，并将数据以串行压缩格式存储在视频控制器的视频存储器中。 视频控制器设置有解压缩电路，以将运动视频数据解压缩为亮度和色差差数据。 亮度和色差差数据被转换成RGB数据并显示在视频显示器中。