公开(公告)号：WO1996030949A1

公开(公告)日：1996-10-03

申请号：PCT/US1996004331

申请日：1996-03-28

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  KESHTOBD, Parviz

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate (42) and the bit line (46) during programming. The erase operation is done by tunneling of electrons from the sharp tip of the floating gate (42) to the control gate (38) through a tunneling insulator layer (50). The floating gate (42) is formed adjacent a sidewall of a bit layer (46) which is preferably formed of tungsten or tungsten alloy. The cell is adapted so that the source (32) for each cell within the array is the source of an adjacent cell and the drain (34) is the drain to another adjacent cell. A method of manufacturing the above EPROM cell is also described.

Abstract translation: 闪存EPROM单元通过在编程期间在浮动栅极（42）和位线（46）之间提供垂直耦合而具有减小的单元尺寸。 擦除操作是通过将隧道绝缘层（50）从电荷从浮栅（42）的尖端引到控制栅（38）的方式进行的。 浮动栅极（42）形成在位于优选由钨或钨合金形成的位层（46）的侧壁附近。 单元适于使得阵列内的每个单元的源极（32）是相邻单元的源极，而漏极（34）是到另一相邻单元的漏极。 还描述了制造上述EPROM单元的方法。