公开(公告)号：EP0910195B1

公开(公告)日：2005-12-14

申请号：EP98307556.5

申请日：1998-09-17

Applicant: Compaq Computer Corporation

Inventor： Witkowski, Michael L. ,  Mayer, Dale J. ,  Walker, William J. ,  Roller, Kirk D. ,  Hareski, Patricia E. ,  Kotzur, Gary B.

IPC: H04L12/46 ,  H04L29/00 ,  H04L12/44

CPC classification number: H04L12/467 ,  H04L49/201 ,  H04L49/205 ,  H04L49/254 ,  H04L49/351 ,  H04L49/354 ,  H04L69/14

公开(公告)号：EP0884872A3

公开(公告)日：1999-06-16

申请号：EP97310664.4

申请日：1997-12-30

Applicant: Compaq Computer Corporation

Inventor： Kotzur, Gary B. ,  Mayer, Dale J. ,  Witkowski, Michael L. ,  Walker, William J. ,  Hareski, Patricia E.

IPC: H04L12/44 ,  H04L12/46 ,  H04L12/56

CPC classification number: H04L49/351 ,  H04L49/201 ,  H04L49/354

Abstract: A network switch including a separate cut-through buffer for facilitating cut-through mode of data transfer. The switch further includes a data bus coupled to each of the ports, a memory and a switch manager coupled to the data bus and to the memory for controlling data flow. The switch manager includes a receive buffer for handling data received by the switch, a transmit buffer for handling data to be transmitted by the switch, and a separate cut-through buffer for receiving data at any of the ports and for buffering the data to another one of the ports during cut-through mode of operation. The switch manager includes status memory, which includes programmable receive and transmit mode values for each of the ports, the modes selecting between cut-through and store-and-forward mode of operation for an indicated direction for each port. Control logic operates source and destination ports in cut-through mode if the receive mode value of the source port and the transmit mode value of the destination port have both been programmed to select cut-through mode.

公开(公告)号：EP0854611A3

公开(公告)日：1999-06-16

申请号：EP97310656.0

申请日：1997-12-30

Applicant: Compaq Computer Corporation

Inventor： Walker, William J. ,  Kotzur, Gary B. ,  Hareski, Patricia E. ,  Mayer, Dale J. ,  Witkowski, Michael L.

IPC: H04L12/44 ,  H04L12/40 ,  H04L12/56

CPC classification number: H04L49/351 ,  H04L49/201 ,  H04L49/205 ,  H04L49/254 ,  Y10S370/911

Abstract: A network switch including one or more network ports for receiving and transmitting data, where each port includes a network interface, a data bus interface and a processor port interface. a data bus coupled to the data bus interface of each of the ports, a processor bus coupled to a processor and to the processor port interface of each of the ports, and a memory bus coupled to a memory. The network switch further includes a switch manager coupled to the data bus, the processor bus and the memory bus for controlling data flow between the ports and said memory and for enabling the processor access to the ports and the memory. In this manner, the processor has direct and relatively independent access to the network ports for performing overhead functions, such as monitoring, determining status and configuration without consuming valuable bandwidth of the data bus.

公开(公告)号：EP0854608A3

公开(公告)日：1999-06-16

申请号：EP97310676.8

申请日：1997-12-30

Applicant: Compaq Computer Corporation

Inventor： Mayer, Dale J. ,  Richter, Roger ,  Witkowski, Michael L. ,  Kotzur, Gary B. ,  Hareski, Patricia E. ,  Walker, William J.

IPC: H04L12/28

CPC classification number: H04L49/103 ,  H04L49/201 ,  H04L49/205 ,  H04L49/254 ,  H04L49/351

Abstract: A network switch including a central memory that stores device identification information, port numbers, control information, and packet data received at the ports of the switch. The memory includes a packet section that stores packet data and a device identification section that stores identification entries, where each entry corresponds to a network device coupled to a port of the switch. The switch includes a switch manager to control data flow between the ports and the central memory. Each of the identification entries includes a unique network address to identify one of the network devices and a port number to identify one of the network ports. Each of the identification entries is located within the central memory at a hash address derived by hashing the unique network address. Hash logic receives and hashes each network address to determine a hash address, which is used to access the identification entries. The memory is organized into a chain structure to enable quick access of entries. The switch manager further includes a control memory for storing control registers, including a freepool control register for identifying a freepool chain of memory sectors, a receive control register for identifying a corresponding receive sector chain and a transmit control register for identifying a corresponding transmit packet chain for each of the ports.

公开(公告)号：EP0854606A3

公开(公告)日：1999-06-16

申请号：EP97310652.9

申请日：1997-12-30

Applicant: Compaq Computer Corporation

Inventor： Hareski, Patricia E. ,  Walker, William J. ,  Kotzur, Gary B. ,  Mayer, Dale J. ,  Witkowski, Michael L.

IPC: H04L12/24 ,  H04L12/44 ,  H04L12/40 ,  H04L12/56

CPC classification number: H04L41/26 ,  H04L41/046 ,  H04L41/24 ,  H04L49/201 ,  H04L49/351 ,  H04L49/354

Abstract: A network switch including a plurality of network ports for receiving and transmitting data, where each port includes at least one statistics register for storing statistics information, such as Ethernet statistical and configuration information. The switch also includes a switch manager, which further includes a memory, retrieval logic for detecting a statistics request signal and for respondingly retrieving the statistics information for storage in the memory, and response logic for asserting a statistics response signal after the statistics information is stored. A processor is coupled to the switch manager through a bus, where the processor asserts the statistics request signal and then detects assertion of the statistics response signal. Upon detecting the response signal, the processor retrieves the statistics information from the memory. In this manner, the processor is removed from direct connection to the statistics registers and free to complete other tasks while the information is being gathered by the switch manager, thereby increasing the efficiency of the processor and of the network switch. Each port preferably includes a network interface, a processor port interface for enabling the switch manager to retrieve the statistical information, and a data bus interface for network traffic. The switch manager thus includes two separate bus connections to each of the ports, so that statistical reads do not interfere with network data packet flow.

公开(公告)号：EP0854614A2

公开(公告)日：1998-07-22

申请号：EP97310665.1

申请日：1997-12-30

Applicant: Compaq Computer Corporation

Inventor： Kotzur, Gary B. ,  Hareski, Patricia E. ,  Witkowski, Michael L. ,  Mayer, Dale J. ,  Walker, William J.

IPC: H04L12/44 ,  H04L29/04 ,  H04L12/40 ,  H04L12/56

CPC classification number: H04L49/254 ,  H04L45/745 ,  H04L49/205 ,  H04L49/351 ,  Y10S370/911

Abstract: A programmable arbitration system including control logic to select one of several arbitration schemes for selecting the ports of a network switch, a memory to store priority values indicating the relative priority of each of the ports, monitor logic to monitor each of the ports and to program the priority values in the memory based on a priority scheme selected by the control logic, and arbitration logic to select a port having the next highest priority. The arbitration schemes preferably include a round-robin priority scheme, a first-come, first-served (FCFS) priority scheme, a weighted priority scheme, or any other desirable priority scheme. The monitor logic includes polling logic to periodically poll the ports and to program a priority value of each port. The memory includes receive and transmit lists to indicate of which of the ports have indicated needing service and a corresponding priority value. The arbitration logic includes a receive arbiter and a transmit arbiter, each of which use a corresponding arbitration count.

Abstract translation: 一种可编程仲裁系统，包括用于选择网络交换机的端口的若干仲裁方案之一的控制逻辑，存储指示每个端口的相对优先级的优先级值的存储器，监控每个端口的监视逻辑和编程 基于由控制逻辑选择的优先级方案的存储器中的优先级值，以及用于选择具有下一最高优先级的端口的仲裁逻辑。 仲裁方案优选地包括循环优先方案，先来先服务（FCFS）优先权方案，加权优先方案或任何其它所需优先权方案。 监视器逻辑包括轮询逻辑以定期轮询端口并编程每个端口的优先级值。 存储器包括接收和发送列表，以指示哪些端口指示需要服务和相应的优先级值。 仲裁逻辑包括接收仲裁器和发送仲裁器，每个仲裁器使用相应的仲裁计数。

公开(公告)号：EP0854608A2

公开(公告)日：1998-07-22

申请号：EP97310676.8

申请日：1997-12-30

Applicant: Compaq Computer Corporation

Inventor： Mayer, Dale J. ,  Richter, Roger ,  Witkowski, Michael L. ,  Kotzur, Gary B. ,  Hareski, Patricia E. ,  Walker, William J.

IPC: H04L12/28

CPC classification number: H04L49/103 ,  H04L49/201 ,  H04L49/205 ,  H04L49/254 ,  H04L49/351

Abstract: A network switch including a central memory that stores device identification information, port numbers, control information, and packet data received at the ports of the switch. The memory includes a packet section that stores packet data and a device identification section that stores identification entries, where each entry corresponds to a network device coupled to a port of the switch. The switch includes a switch manager to control data flow between the ports and the central memory. Each of the identification entries includes a unique network address to identify one of the network devices and a port number to identify one of the network ports. Each of the identification entries is located within the central memory at a hash address derived by hashing the unique network address. Hash logic receives and hashes each network address to determine a hash address, which is used to access the identification entries. The memory is organized into a chain structure to enable quick access of entries. The switch manager further includes a control memory for storing control registers, including a freepool control register for identifying a freepool chain of memory sectors, a receive control register for identifying a corresponding receive sector chain and a transmit control register for identifying a corresponding transmit packet chain for each of the ports.

Abstract translation: 一种网络交换机，包括存储在交换机的端口处接收的设备标识信息，端口号，控制信息和分组数据的中央存储器。 存储器包括存储分组数据的分组部分和存储标识条目的设备标识部分，其中每个条目对应于耦合到交换机的端口的网络设备。 交换机包括一个交换机管理器来控制端口和中央存储器之间的数据流。 每个标识条目包括唯一的网络地址以识别网络设备之一和用于识别其中一个网络端口的端口号。 每个识别条目位于中央存储器内的哈希地址处，通过散列唯一的网络地址而导出。 散列逻辑接收和散列每个网络地址以确定用于访问标识条目的散列地址。 存储器被组织成链结构以便能够快速访问条目。 开关管理器还包括用于存储控制寄存器的控制存储器，包括用于识别存储器扇区的freepool链的freepool控制寄存器，用于识别对应的接收扇区链的接收控制寄存器和用于识别对应的发送分组链的发送控制寄存器 为每个端口。