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    Circuit for reassigning the power-on processor in a multiprocessing system
    2.
    发明公开
    Circuit for reassigning the power-on processor in a multiprocessing system 失效
    电路的重新分配在多处理器系统中的Einschaltsprozessors

    公开(公告)号：EP0720094A3

    公开(公告)日：1997-04-23

    申请号：EP95309547.8

    申请日：1995-12-29

    Applicant: Compaq Computer Corporation

    Inventor： Goodrum, Alan A. ,  Kotzur, Gary B. ,  Lantz, Kurt C. ,  Heinrich, David F. ,  Wilson, Jeffrey R.

    IPC: G06F11/00 ,  G06F15/16

    CPC classification number: G06F15/177 ,  G06F1/26 ,  G06F11/1417

    Abstract: A hot spare boot circuit that automatically switches from a non-operational CPU to an operational CPU for powering up the computer system. In the multiprocessor computer system, a first CPU is designated to perform power on operations. If the first CPU fails, which is determined when a dead man counter in the hot spare boot circuit times out, the hot spare circuit ensures that the first CPU is in a disabled state. Next, the hot spare boot circuit identifies an operational second CPU, reinitializing certain ID information as necessary such that the second CPU can properly perform power on operations. The hot spare boot then awakens the second CPU, using a startup interprocessor interrupt in one embodiment, or simply negating the hard reset of the second CPU in a second embodiment. The second CPU then proceeds to perform the power on functions.

    Method and system for performing concurrent read and write cycles in a network switch
    6.
    发明公开
    Method and system for performing concurrent read and write cycles in a network switch 失效
    方法和系统，用于在网络交换结构同时执行读和写周期

    公开(公告)号：EP0854612A3

    公开(公告)日：1999-06-16

    申请号：EP97310662.8

    申请日：1997-12-30

    Applicant: Compaq Computer Corporation

    Inventor： Walker, William J. ,  Kotzur, Gary B. ,  Hareski, Patricia E. ,  Witkowski, Michael L. ,  Mayer, Dale J.

    IPC: H04L12/44 ,  H04L29/04 ,  H04L12/40 ,  H04L12/56

    CPC classification number: H04L49/351 ,  H04L49/254 ,  H04L49/354

    Abstract: A system for performing concurrent read and write cycles in a network switch. The network switch includes several network ports, a data bus and a switch manager to execute a concurrent read and write cycle on the data bus by asserting a first port number to identify a source port followed by a second port number to identify a destination port. Each of the ports includes a network interface for sending and receiving data packets and a data interface to store the first port number, to assert data received from the network interface onto the data bus if that port is identified by the first port number, and to retrieve data from the data bus for transmission by the network interface if that port is identified by the second port number. In this manner, data is transferred directly between a source and a destination port without being buffered in the switch manager. The bandwidth of the data bus is increased since data is transferred only once on the data bus. Latches are provided for the ports to latch the read port number to allow that write port number to be asserted during the cycle. A method of executing a concurrent read and write cycle includes the steps of asserting a first port number to identify a source port, latching the first port number, asserting a second port number to identify a destination port, and concurrently writing and reading the data on the data bus.

    Network switch with statistics read accesses
    7.
    发明公开
    Network switch with statistics read accesses 失效
    Netzwerkkoppelfeld mit Lesezugriffen auf Statistiken

    公开(公告)号：EP0854606A2

    公开(公告)日：1998-07-22

    申请号：EP97310652.9

    申请日：1997-12-30

    Applicant: Compaq Computer Corporation

    Inventor： Hareski, Patricia E. ,  Walker, William J. ,  Kotzur, Gary B. ,  Mayer, Dale J. ,  Witkowski, Michael L.

    IPC: H04L12/24 ,  H04L12/44 ,  H04L12/40 ,  H04L12/56

    CPC classification number: H04L41/26 ,  H04L41/046 ,  H04L41/24 ,  H04L49/201 ,  H04L49/351 ,  H04L49/354

    Abstract: A network switch including a plurality of network ports for receiving and transmitting data, where each port includes at least one statistics register for storing statistics information, such as Ethernet statistical and configuration information. The switch also includes a switch manager, which further includes a memory, retrieval logic for detecting a statistics request signal and for respondingly retrieving the statistics information for storage in the memory, and response logic for asserting a statistics response signal after the statistics information is stored. A processor is coupled to the switch manager through a bus, where the processor asserts the statistics request signal and then detects assertion of the statistics response signal. Upon detecting the response signal, the processor retrieves the statistics information from the memory. In this manner, the processor is removed from direct connection to the statistics registers and free to complete other tasks while the information is being gathered by the switch manager, thereby increasing the efficiency of the processor and of the network switch. Each port preferably includes a network interface, a processor port interface for enabling the switch manager to retrieve the statistical information, and a data bus interface for network traffic. The switch manager thus includes two separate bus connections to each of the ports, so that statistical reads do not interfere with network data packet flow.

    Abstract translation: 一种网络交换机，包括用于接收和发送数据的多个网络端口，其中每个端口包括至少一个用于存储诸如以太网统计信息和配置信息的统计信息的统计寄存器。 交换机还包括开关管理器，其还包括存储器，用于检测统计信号请求信号的检索逻辑和用于响应地检索用于存储在存储器中的统计信息，以及用于在存储统计信息之后断言统计响应信号的响应逻辑 。 处理器通过总线耦合到交换机管理器，其中处理器断言统计请求信号，然后检测统计响应信号的断言。 在检测到响应信号时，处理器从存储器检索统计信息。 以这种方式，处理器从直接连接到统计寄存器被移除，并且在交换管理器收集信息的同时可以自由地完成其他任务，从而提高处理器和网络交换机的效率。 每个端口优选地包括网络接口，用于使交换机管理器能够检索统计信息的处理器端口接口和用于网络业务的数据总线接口。 因此，交换管理器包括到每个端口的两个单独的总线连接，使得统计读取不会干扰网络数据分组流。

    A programmable arbitration system for determining priority of the ports of a network switch
    9.
    发明公开
    A programmable arbitration system for determining priority of the ports of a network switch 失效
    用于确定网络交换网络的栅极的优先可编程仲裁系统

    公开(公告)号：EP0854614A3

    公开(公告)日：1999-06-16

    申请号：EP97310665.1

    申请日：1997-12-30

    Applicant: Compaq Computer Corporation

    Inventor： Kotzur, Gary B. ,  Hareski, Patricia E. ,  Witkowski, Michael L. ,  Mayer, Dale J. ,  Walker, William J.

    IPC: H04L12/44 ,  H04L29/04 ,  H04L12/40 ,  H04L12/56

    CPC classification number: H04L49/254 ,  H04L45/745 ,  H04L49/205 ,  H04L49/351 ,  Y10S370/911

    Abstract: A programmable arbitration system including control logic to select one of several arbitration schemes for selecting the ports of a network switch, a memory to store priority values indicating the relative priority of each of the ports, monitor logic to monitor each of the ports and to program the priority values in the memory based on a priority scheme selected by the control logic, and arbitration logic to select a port having the next highest priority. The arbitration schemes preferably include a round-robin priority scheme, a first-come, first-served (FCFS) priority scheme, a weighted priority scheme, or any other desirable priority scheme. The monitor logic includes polling logic to periodically poll the ports and to program a priority value of each port. The memory includes receive and transmit lists to indicate of which of the ports have indicated needing service and a corresponding priority value. The arbitration logic includes a receive arbiter and a transmit arbiter, each of which use a corresponding arbitration count.

    Network switch with separate cut-through buffer
    10.
    发明公开
    Network switch with separate cut-through buffer 失效
    Netzwerkkoppelfeld mit getrenntem Durchgangspuffer

    公开(公告)号：EP0884872A2

    公开(公告)日：1998-12-16

    申请号：EP97310664.4

    申请日：1997-12-30

    Applicant: Compaq Computer Corporation

    Inventor： Kotzur, Gary B. ,  Mayer, Dale J. ,  Witkowski, Michael L. ,  Walker, William J. ,  Hareski, Patricia E.

    IPC: H04L12/44 ,  H04L12/46 ,  H04L12/56

    CPC classification number: H04L49/351 ,  H04L49/201 ,  H04L49/354

    Abstract: A network switch including a separate cut-through buffer for facilitating cut-through mode of data transfer. The switch further includes a data bus coupled to each of the ports, a memory and a switch manager coupled to the data bus and to the memory for controlling data flow. The switch manager includes a receive buffer for handling data received by the switch, a transmit buffer for handling data to be transmitted by the switch, and a separate cut-through buffer for receiving data at any of the ports and for buffering the data to another one of the ports during cut-through mode of operation. The switch manager includes status memory, which includes programmable receive and transmit mode values for each of the ports, the modes selecting between cut-through and store-and-forward mode of operation for an indicated direction for each port. Control logic operates source and destination ports in cut-through mode if the receive mode value of the source port and the transmit mode value of the destination port have both been programmed to select cut-through mode.

    Abstract translation: 一种网络交换机，包括一个独立的直通缓冲区，用于促进数据传输的直通模式。 开关还包括耦合到每个端口的数据总线，耦合到数据总线的存储器和开关管理器以及用于控制数据流的存储器。 交换机管理器包括用于处理由交换机接收的数据的接收缓冲器，用于处理由交换机发送的数据的发送缓冲器，以及用于在任何端口接收数据并用于将数据缓冲到另一个端口的单独的直通缓冲器 其中一个端口在直通操作模式下。 交换机管理器包括状态存储器，其包括每个端口的可编程接收和发送模式值，所述模式在每个端口的指示方向的切换和存储转发操作模式之间进行选择。 如果源端口的接收模式值和目标端口的发送模式值都被编程为选择直通模式，则控制逻辑将以切入模式运行源端口和目标端口。

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