公开(公告)号：AU3138693A

公开(公告)日：1993-06-15

申请号：AU3138693

申请日：1992-11-16

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： STEVEN E FAIRCHILD ,  MICHAEL R GEROCHE ,  MARK T LUNDGREEN ,  BENNY J KLINGSPORN

IPC: G06F3/06 ,  G06F11/00 ,  G06F11/22 ,  G06F11/267 ,  G06F11/34 ,  G06F12/16 ,  G11B20/18

Abstract: A dynamic testing method for determining disk drive error rates based on the number of bytes which are read from a hard disk drive during test. The method identifies specific faulting disk sectors and disk error types and maintains a log of the errors. The method also accumulates the total number of bytes which have been read from the disk and determines whether the disk under test has exceeded acceptable error rates based on the number of bytes read during the test. This permits the method to identify a disk drive as having failed its test prior to completion of the full disk drive test cycle.

公开(公告)号：AU638381B2

公开(公告)日：1993-06-24

申请号：AU2102692

申请日：1992-08-13

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： JOHN R. PIES ,  DAVID B. WALLACE ,  DONALD J. HAYES

IPC: B41J2/015 ,  B41J2/045 ,  B41J2/055 ,  B41J2/14 ,  B41J2/16

Abstract: A sidewall actuated channel array for a high density ink jet printhead. The sidewall actuator (28) includes a top wall (16), a bottom wall (12) and at least one elongated liquid confining channel (18) defined by the top wall (16), the bottom wall (12) and sidewalls (30,32). The actuator sidewall is comprised of a first actuator sidewall section (32) formed of a piezoelectric material poled in a first direction perpendicular to a first channel (18) and attached to the top wall (16), a second actuator sidewall section (30) attached to the first sidewall section (32) and the bottom wall (12), and means for applying an electric field across the first actuator sidewall section (32) and perpendicular to the direction of polarization. When the electric field is applied across the first sidewall section (32), the actuator sidewall engages in a motion which produces an ink ejecting pressure pulse in the channel (18).

公开(公告)号：AU2102592A

公开(公告)日：1993-03-04

申请号：AU2102592

申请日：1992-08-13

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： JOHN R. PIES ,  DAVID B. WALLACE ,  DONALD J. HAYES

IPC: B41J2/045 ,  B41J2/055 ,  B41J2/14 ,  B41J2/15 ,  B41J2/155 ,  B41J2/16 ,  B41J2/21

Abstract: An ink jet printhead (10) for a drop-on-demand type ink jet printing system. The printhead includes a base section (12) having a series of generally parallel spaced projections (30) extending longitudinally therealong, a series of intermediate sections (32) conductively mounted on a top side of a corresponding one of the series of base section projections (30) and a top section (16) conductively mounted to a top side of each of the series of intermediate sections (32).

公开(公告)号：AU2102692A

公开(公告)日：1993-02-25

申请号：AU2102692

申请日：1992-08-13

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： JOHN R. PIES ,  DAVID B. WALLACE ,  DONALD J. HAYES

IPC: B41J2/015 ,  B41J2/045 ,  B41J2/055 ,  B41J2/14 ,  B41J2/16

Abstract: A sidewall actuated channel array for a high density ink jet printhead. The sidewall actuator (28) includes a top wall (16), a bottom wall (12) and at least one elongated liquid confining channel (18) defined by the top wall (16), the bottom wall (12) and sidewalls (30,32). The actuator sidewall is comprised of a first actuator sidewall section (32) formed of a piezoelectric material poled in a first direction perpendicular to a first channel (18) and attached to the top wall (16), a second actuator sidewall section (30) attached to the first sidewall section (32) and the bottom wall (12), and means for applying an electric field across the first actuator sidewall section (32) and perpendicular to the direction of polarization. When the electric field is applied across the first sidewall section (32), the actuator sidewall engages in a motion which produces an ink ejecting pressure pulse in the channel (18).

公开(公告)号：AU1855792A

公开(公告)日：1993-01-07

申请号：AU1855792

申请日：1992-06-24

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： CHARLES A. SELLERS ,  STEVE J. LAU

IPC: B65H3/44 ,  G03G15/00

Abstract: A paper feed system for an image reproduction machine, representatively a printer, has a shelf member (44) disposed within the machine housing and rotatably carrying a turntable (76) on its upper side. Two transversely oriented pairs of diametrically opposite upper and lower paper trays (136,138;100,102) are removably supported on the turntable, with portions of the upper trays overlying the lower trays. The turntable may be rotated to vertically interpose a selected one of the four trays between a stationary picker roller (36) and a lifter structure (140) positioned beneath the picker roller. The lifter structure has a portion which moves upwardly through a shelf opening, and a turntable opening aligned therewith, to engage the selected tray and lift it toward the picker roller to bring a paper stack held in the tray into engagement with the picker roller which operates to successively remove sheets from the stack and deliver them to the machine's paper feed path. The lifter structure may then be lowered to return the selected tray to its initial position on the turntable and permit another tray to be selected for rotation into a position from which it may be lifted to the picker roller. When a lower tray is selected, a shift mechanism (122-126) is operated to move the upper trays out of the lift path of the selected lower tray. The trays may be accessed by operating a drive motor (54) which drives the turntable shelf horizontally outwardly through a housing side wall access opening.

公开(公告)号：WO1995010092A1

公开(公告)日：1995-04-13

申请号：PCT/US1994011379

申请日：1994-10-05

Applicant: NSOFT SYSTEMS, INC. ,  COMPAQ COMPUTER CORPORATION

Inventor： NSOFT SYSTEMS, INC. ,  COMPAQ COMPUTER CORPORATION ,  LEE, Ven, L. ,  DAWSON, William, M. ,  DOUD, Donald, L.

IPC: G06F17/50

CPC classification number: H01L27/11803 ,  G06F17/5068 ,  H01L27/118

Abstract: In accordance with this invention, matched performance of alternate sourced ASICs is achieved while still allowing for the smallest die size possible from each alternate source fabrication facility. In one aspect of this invention, the width of electrical interconnects (Wm1, Wm2) are adjusted to compensate for differences in capacitances of a given interconnect path in devices fabricated by different fabrication facilities. In another aspect, transistor channel widths (Wpd, Wnd) are adjusted to compensate for differences in capacitances of a given interconnect path in devices fabricated by different fabrication facilities. In yet another aspect of this invention, capacitance is added to the gates of transistors to decrease their speed, when manufactured by an inherently faster process.

Abstract translation: 根据本发明，实现了替代源ASIC的匹配性能，同时仍然允许来自每个替代源制造设施的最小管芯尺寸。 在本发明的一个方面中，电气互连的宽度（Wm1，Wm2）被调整以补偿由不同的制造设备制造的器件中给定的互连路径的电容的差异。 在另一方面，调整晶体管沟道宽度（Wpd，Wnd）以补偿由不同制造设备制造的器件中的给定互连路径的电容差。 在本发明的另一方面，当通过固有更快的工艺制造时，电容被添加到晶体管的栅极以降低它们的速度。

公开(公告)号：WO1995001611A1

公开(公告)日：1995-01-12

申请号：PCT/US1994007583

申请日：1994-06-30

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  SELLERS, Charles, A.

IPC: G06K11/18

CPC classification number: G06F1/1662 ,  G06F1/1616 ,  G06F1/169 ,  G06F3/0213

Abstract: A computer having a keyboard unit with a spacebar wherein a trackball module is mounted within the spacebar for ease of access by left-handed or right-handed persons. The trackball module is mounted intermediately of the spacebar. In one embodiment, the trackball module is mounted for movement with a spacebar and in another embodiment, the trackball module is stationary such that the spacebar moves upwardly and downwardly relative to the trackball module.

Abstract translation: 具有带空格键的键盘单元的计算机，其中轨迹球模块安装在空格键内，以便左手或右撇子人易于进入。 轨迹球模块安装在空格键的中间。 在一个实施例中，轨迹球模块被安装成与空格键一起移动，并且在另一个实施例中，轨迹球模块是静止的，使得空格键相对于轨迹球模块向上和向下移动。

公开(公告)号：WO1994011998A1

公开(公告)日：1994-05-26

申请号：PCT/US1993010907

申请日：1993-11-08

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  NAGEL, Paul, E. ,  CASTELL, Robin, T.

IPC: H04Q07/04

CPC classification number: H04W88/02 ,  H04M11/06 ,  Y02D70/00

Abstract: A modem (12) is incorporated into a laptop computer (10) and directly connected to either a cellular phone (22), a land line (18), or both. The modem is provided with two connectors (14, 16), one for connection with a cellular phone or external DAA (24), the other for connection to a normal land line via an internal DAA (112). The modem selectively enables either the connector for the cellular phone or external DAA, or the connector for its internal DAA. The modem defaults to selecting the cellular phone or external DAA if it is connected, and only if they are not connected selects the internal DAA. These defaults can be overridden by user commands. Further, the modem can independently power down a connected internal DAA, external DAA, or cellular phone to conserve power.

Abstract translation: 调制解调器（12）被并入到膝上型计算机（10）中并且直接连接到蜂窝电话（22），陆线（18）或两者。 调制解调器具有两个连接器（14,16），一个用于与蜂窝电话或外部DAA（24）连接，另一个用于通过内部DAA（112）连接到正常的陆线。 调制解调器选择性地启用用于蜂窝电话或外部DAA的连接器，或用于其内部DAA的连接器。 调制解调器默认选择手机或外部DAA（如果已连接），并且只有在未连接时才选择内部DAA。 这些默认值可以被用户命令覆盖。 此外，调制解调器可以独立地断开连接的内部DAA，外部DAA或蜂窝电话以节省电力。

公开(公告)号：WO1994008293A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009431

申请日：1993-09-30

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  LANDRY, John, A. ,  WOLFORD, Jeff, W. ,  FRY, Walter, G. ,  TIPLEY, Roger, E.

IPC: G06F11/20

CPC classification number: G06F11/1637 ,  G06F11/1679

Abstract: A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to the respective processor. The processors on one or more CPU boards are designated as master processors, with the processors on the remaining CPU boards being designated as mirroring or slave processors. A master processor has full access to the host bus and a second, multiplexed bus for read and write cycles, whereas the slave processors are prevented from writing to any bus. The slave processors compare write data and various control signals with that generated by its respective master processor for disparities. The system includes interrupt controller synchronization logic to synchronize interrupt requests as well as timer synchronization logic to synchronize the timers in each of the master and slave CPUs to guarantee that the master and slave CPUs operate in lockstep.

Abstract translation: 一种用于在计算机系统中操作紧耦合的镜像处理器的方法和装置。 多个CPU板耦合到通常称为主机总线的处理器/存储器总线。 每个CPU板包括一个处理器以及各个处理器本地的各种端口，定时器和中断控制器逻辑。 一个或多个CPU板上的处理器被指定为主处理器，其余CPU板上的处理器被指定为镜像或从属处理器。 主处理器具有对主机总线的完全访问和用于读和写周期的第二复用总线，而从处理器被阻止写入任何总线。 从处理器将写入数据和各种控制信号与其相应的主处理器产生的差异进行比较。 该系统包括中断控制器同步逻辑，以同步中断请求以及定时器同步逻辑，以同步每个主CPU和从CPU的定时器，以保证主CPU和从CPU处于锁定状态。

公开(公告)号：WO1993017387A1

公开(公告)日：1993-09-02

申请号：PCT/US1993001548

申请日：1993-02-19

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  STEVENS, Jeffrey, C. ,  RAMSEY, Jens, K. ,  BONELLA, Randy, M. ,  KELLY, Philip, C.

IPC: G06F12/08

CPC classification number: G06F12/0835 ,  G06F12/0811 ,  G06F13/161

Abstract: A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop control logic does not direct the cache to snoop this subsequent access. This eases the snooping burden of the cache and thus increases the efficiency of the processor working out of the cache during this time. When a multilevel cache system is implemented, the snoop control logic directs the cache to snoop certain subsequent accesses to a previously snooped line in order to prevent cache coherency problems from arising. Latency reduction logic which reduces latency problems in the snooping operation of the cache is also included. After every processor read that is transmitted beyond the cache, i.e., cache read misses, the logic gains control of the address inputs of the cache for snooping purposes. The cache no longer needs its address bus for the read cycle and thus the read operation continues unhindered. In addition, the cache is prepared for an upcoming snoop cycle.

Abstract translation: 一种用于减少缓存系统的窥探需求并减少缓存系统中的延迟问题的方法和装置。 当高速缓存发生窥探访问时，如果侦听控制逻辑确定先前的侦听访问涉及同一内存位置行，则侦听控制逻辑不会引导高速缓存窥探此后续访问。 这缓解了缓存的窥探负担，从而提高了在此期间从高速缓存中工作的处理器的效率。 当实现多级缓存系统时，监听控制逻辑引导高速缓存窥探对先前侦听行的某些后续访问，以防止出现高速缓存一致性问题。 还包括减少高速缓存的窥探操作中的延迟问题的延迟降低逻辑。 在每个超出高速缓存的处理器读取，即高速缓存读取未命中之后，逻辑增益用于高速缓存的地址输入的控制用于窥探目的。 缓存不再需要其地址总线用于读取周期，因此读取操作不受阻碍地继续。 此外，高速缓存准备好即将到来的窥探周期。