公开(公告)号：JP2011091543A

公开(公告)日：2011-05-06

申请号：JP2009242402

申请日：2009-10-21

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： TOMINAGA SATOSHI ,  MATSUI YOSHINORI

IPC: H03K19/0175 ,  H03K5/12 ,  H03K5/125 ,  H03K17/687 ,  H03K19/0948

CPC classification number: H03K19/01707 ,  H03K19/0016 ,  H03K19/00384

Abstract: PROBLEM TO BE SOLVED: To reduce difference in propagation speed caused by a transition direction of a signal in a signal transmission circuit. SOLUTION: The signal transmission circuit includes: an inverter which includes transistors 41, 42 connected in series between power supply lines 21 and 22; a source transistor 32 which is provided between the power supply line 22 and the transistor 42 and is put into a state of conductivity based on control signals; and a load transistor 51 which is used as a load circuit provided between the power supply line 21 and the transistor 41. According to this invention, since difference between a load between the power supply line 22 and the transistor 42 and a load between the power supply line 21 and the transistor 41 is reduced, difference between signal propagation speed when an input signal to be supplied to the inverter transitions from a low level to a high level and signal propagation speed when the input signal transitions from the high level to the low level is reduced. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：减少由信号传输电路中的信号的转变方向引起的传播速度的差异。 解决方案：信号传输电路包括：反相器，其包括串联连接在电源线21和22之间的晶体管41,42; 源极晶体管32，其设置在电源线22和晶体管42之间，并且基于控制信号进入导通状态; 以及负载晶体管51，其用作设置在电源线21和晶体管41之间的负载电路。根据本发明，由于电源线22和晶体管42之间的负载与电源之间的负载之间的差异 供给线21和晶体管41减小，当输入到反相器的输入信号从低电平转换到高电平时的信号传播速度差和当输入信号从高电平转变为低电平时的信号传播速度 水平下降。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2003068082A

公开(公告)日：2003-03-07

申请号：JP2001254780

申请日：2001-08-24

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MATSUI YOSHINORI

IPC: G11C11/409 ,  G06F3/00 ,  G06F12/00 ,  G06F13/16 ,  G11C7/10 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/407 ,  H03K19/0175

CPC classification number: G11C7/1063 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066

Abstract: PROBLEM TO BE SOLVED: To provide a memory system in which deterioration of signal quality caused by signal reflection by mismatching of wiring impedance of a data bus is lightened, and which can perform read-out and write-in of data at high speed, in a memory system in which memory devices such as a DRAM or the like are branched for a data bus.
SOLUTION: This system is memory device connected to a data bus, the memory device is provided with an active terminal circuit terminal-controlling this memory device and a control circuit controlling electrically this active terminal circuit to an active state or an inactive state, in it. Further, this memory system has a plurality of memory devices, while has a memory controller performing terminal control of the plurality of memory devices. In this case, also the memory controller is provided with the terminal circuit made an active state or an inactive state.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种存储系统，其中通过数据总线的布线阻抗失配的信号反射引起的信号质量的劣化被减轻，并且可以以高速度执行数据的读出和写入， 存储器系统，其中诸如DRAM等的存储器件被分支用于数据总线。 解决方案：该系统是连接到数据总线的存储器件，存储器件具有控制该存储器件的有源端子电路端子和控制电路，用于将该有源端子电路电激活到活动状态或非活动状态 。 此外，该存储器系统具有多个存储器件，同时具有执行多个存储器件的端子控制的存储器控​​制器。 在这种情况下，存储器控制器还具有使端子电路处于活动状态或非活动状态。

公开(公告)号：JP2003050738A

公开(公告)日：2003-02-21

申请号：JP2001236759

申请日：2001-08-03

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MATSUI YOSHINORI

IPC: G06F12/00 ,  G06F1/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C29/50

CPC classification number: G11C29/12015 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2207/2254

Abstract: PROBLEM TO BE SOLVED: To provide a memory system, capable of achieving reduction of the number of clock signal lines and simultaneously preventing decrease in timing margins on the signal receiving side.
SOLUTION: A memory controller 20 generates an internal clock signal for receiving a DQ signal, based on continuous inversion signals and a reference clock signal by receiving the continuous inversion signals from a DRAM 30
2 as pseudo-clock signals. Next, the memory controller 20 counts the number of clocks of the internal clock for receiving, after an OUT 1 command has been issued to the DRAM 30
2 until reception of a high-level data signal from the DRAM 30
2 as a DQ data signal and holds the counted number as the number of delayed clocks. Thus, the memory controller 20 can receive read data by the internal clock signal for reception, when the number of delayed clocks elapses after a read command has been issued in the case of receiving the read data (DQ signal).
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种能够实现时钟信号线的数量的减少并且同时防止信号接收侧的定时裕度的降低的存储器系统。 解决方案：存储器控制器20通过从DRAM 302接收作为伪时钟信号的连续反转信号，基于连续反转信号和参考时钟信号来产生用于接收DQ信号的内部时钟信号。 接下来，存储器控制器20在向DRAM 302发出OUT 1命令之后，计数用于接收的内部时钟的时钟数，直到从DRAM 302接收到高电平数据信号为DQ数据信号并保持 计数数作为延迟时钟数。 因此，当在接收到读取数据（DQ信号）的情况下已经发出读命令之后，延迟时钟的数量经过时，存储器控制器20可以通过内部时钟信号接收读取数据。

公开(公告)号：JP2011090750A

公开(公告)日：2011-05-06

申请号：JP2009244390

申请日：2009-10-23

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MATSUI YOSHINORI

IPC: G11C11/4096

CPC classification number: G11C5/063 ,  G11C5/025 ,  G11C11/4097

Abstract: PROBLEM TO BE SOLVED: To perform data transfer between hierarchized data lines with low power consumption.
SOLUTION: A semiconductor device is equipped with switch transistors 41 and 42 provided between a sub data line LIO and a main data line MIO. In transferring data, a voltage of VPP level is supplied to gate electrodes of the switch transistors 41 and 42 when these transistors are brought into conduction, and a voltage of VPERI level is supplied to the gate electrodes when these transistors are brought into nonconduction. Since the voltage of the gate electrodes is not lowered to a voltage of VSS level when the switch transistors 41 and 42 are brought into nonconduction, a charge and discharge current of a gate capacitance is reduced. Since the voltage of VPP level is supplied when the switch transistors 41 and 42 are brought into conduction, a voltage level after data transfer does not decrease by a threshold voltage.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：以低功耗执行层次化数据线之间的数据传输。 解决方案：半导体器件配备有设置在子数据线LIO和主数据线MIO之间的开关晶体管41和42。 在传送数据时，当这些晶体管导通时，将VPP电平的电压提供给开关晶体管41和42的栅电极，并且当这些晶体管进行非导通时，将VPERI电平的电压提供给栅电极。 由于当开关晶体管41和42不被导通时，栅电极的电压不降低到VSS电平的电压，所以栅极电容的充放电电流减小。 由于当开关晶体管41和42导通时提供VPP电平的电压，所以数据传输之后的电压电平不会降低阈值电压。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2008293604A

公开(公告)日：2008-12-04

申请号：JP2007139104

申请日：2007-05-25

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MATSUI YOSHINORI

IPC: G11C11/4093 ,  H03K19/0175

CPC classification number: G11C7/1051 ,  G11C7/1057

Abstract: PROBLEM TO BE SOLVED: To provide an output circuit of a semiconductor memory device capable of suppressing a leak current in standby and also reducing current consumption in operation.
SOLUTION: The output circuit includes an inverter INV (1), in which a PMOS transistor Q11 and a NMOS transistor Q21 are connected in series, and read-out data OUTHB from a memory cell is logic-reversed to output a gate signal of a PMOS transistor 51 for output. In the standby, a PMOS transistor Q81 is turned on, a power source VDD (1.8 V) is selected as a circuit power source of the inverter INV (1), and a gate level of the PMOS transistor Q51 for output is set to the VDD level. In the operation, an NMOS transistor Q71 is turned on, a power source VDDQ (1.2 V) is selected, and a gate level of the PMOS transistor Q51 is set to a VDDQ level.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供能够抑制待机时的泄漏电流的半导体存储器件的输出电路，并且还降低工作中的电流消耗。 解决方案：输出电路包括其中PMOS晶体管Q11和NMOS晶体管Q21串联连接的反相器INV（1），并且来自存储单元的读出数据OUTHB被逻辑反转以输出栅极 用于输出的PMOS晶体管51的信号。 在待机状态下，PMOS晶体管Q81导通，选择电源VDD（1.8V）作为反相器INV（1）的电路电源，将用于输出的PMOS晶体管Q51的栅极电平设定为 VDD电平。 在该操作中，NMOS晶体管Q71导通，选择电源VDDQ（1.2V），PMOS晶体管Q51的栅极电平设定为VDDQ电平。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008123543A

公开(公告)日：2008-05-29

申请号：JP2007333155

申请日：2007-12-25

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MATSUI YOSHINORI

IPC: G06F12/00 ,  G06F13/16

Abstract: PROBLEM TO BE SOLVED: To provide a memory system by which a high-speed operation between a memory controller and a memory module can be achieved. SOLUTION: In the memory system comprising the memory controller and a memory module mounted with DRAMs, a buffer is mounted on the memory module, the buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring, the DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and clock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules and to cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供可以实现存储器控制器和存储器模块之间的高速操作的存储器系统。 解决方案：在包括存储器控制器和安装有DRAM的存储器模块的存储器系统中，缓冲器安装在存储器模块上，缓冲器和存储器控制器通过数据线，命令/地址布线相互连接， 并且时钟接线，DRAM和存储器模块上的缓冲器通过内部数据接线，内部命令/地址接线和时钟接线相互连接。 数据线，命令/地址线和时钟接线可以连接到其他存储器模块的缓冲器并级联。 在DRAM和存储器模块的缓冲器之间，使用与时钟同步的数据相位信号实现高速数据传输。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2006323878A

公开(公告)日：2006-11-30

申请号：JP2006244275

申请日：2006-09-08

Applicant: ELPIDA MEMORY INC

Inventor： MATSUI YOSHINORI

IPC: G06F12/00

Abstract: PROBLEM TO BE SOLVED: To solve a problem wherein, with transmission/reception timing of a data signal and that of a clock/address signal different from each other depending on the difference between topologies in a memory system, the topology of clock/command address wiring is different from that of data wiring in relation to a memory system having a structure with a plurality of DRAMs arranged in each of a plurality of modules; and each DRAM is connected to a memory controller (MC) by data wiring and clock wiring. SOLUTION: Since the data signal provided via the data wiring and a clock/command address signal provided via the clock wiring/command address wiring are transmitted and received in the DRAMs and the MC at distinct timing, circuits for matching the timing are arranged in the DRAMs and the MC. In addition, after a phase for a clock signal of the data signal is retained, the memory controller periodically generates sampling clocks; and also the phase of the data signal is adjusted according to the sampling clocks after the phase retention in the DRAMs. COPYRIGHT: (C)2007,JPO&INPIT

公开(公告)号：JP2006172526A

公开(公告)日：2006-06-29

申请号：JP2004359233

申请日：2004-12-10

Applicant: Elpida Memory Inc ,  Hitachi Ulsi Systems Co Ltd ,  エルピーダメモリ株式会社 ,  株式会社日立超エル・エス・アイ・システムズ

Inventor： TANAKA HITOSHI ,  KAJITANI KAZUHIKO ,  MATSUI YOSHINORI ,  YAMAMOTO AKIRA ,  ONODERA TADASHI

IPC: G11C11/406 ,  G11C11/407

CPC classification number: G11C11/406 ,  G11C11/40615

Abstract: PROBLEM TO BE SOLVED: To provide a self refresh timer circuit which generates a timer period which is changed relative to temperature continuously and in terms of index function and, which is suitable for usage under a condition that ambient temperature is changed. SOLUTION: The self refresh timer circuit comprises a bias current circuit 11 for supplying a bias current to each part; a temperature dependence voltage source 12 for outputting a voltage to which temperature dependence based on a diode characteristic is granted; a control current generating circuit 13 having a constant current source 13b so as to generate a control current I' which is proportional to a current I flowing by applying the output voltage of the temperature dependence voltage source 12; a current control oscillation circuit 14 for generating the oscillation signal of the period which is inversely proportional to the largeness of the control current I'; and a frequency dividing circuit 15 for dividing the frequency of the oscillation signal and outputting a timer periodic signal. The output voltage level of the temperature dependence voltage source 12 and the largeness of the control current are appropriately adjusted, so as to generate the timer period which meets the temperature characteristic of an information holding time. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种自刷新定时器电路，其生成相对于温度连续地变化的定时周期，并且在索引函数方面，适合于在环境温度变化的条件下使用。 解决方案：自刷新定时器电路包括用于向每个部分提供偏置电流的偏置电流电路11; 用于输出基于二极管特性的温度依赖性的电压的温度依赖性电压源12; 具有恒流源13b的控制电流产生电路13，以通过施加温度依赖性电压源12的输出电压产生与流过的电流I成比例的控制电流I'; 用于产生与控制电流I'的大小成反比的周期的振荡信号的电流控制振荡电路14; 以及分频电路15，用于分频振荡信号的频率并输出定时器周期信号。 适当地调节温度依赖性电压源12的输出电压电平和控制电流的大小，以产生满足信息保持时间的温度特性的定时器周期。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2013118033A

公开(公告)日：2013-06-13

申请号：JP2011265684

申请日：2011-12-05

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： ITO HIROSHI ,  MATSUI YOSHINORI

IPC: G11C11/4076 ,  G11C11/407 ,  H03K5/00

CPC classification number: G11C7/22 ,  G11C7/1093 ,  G11C7/222

Abstract: PROBLEM TO BE SOLVED: To perform an accurate write leveling operation.SOLUTION: A semiconductor device comprises for example: a divider circuit 100 that generates a plurality of frequency-division clock signals PCLK0-n having phases different from each other by frequency-dividing an external clock signal CK; a multiplier circuit 200 that generates an internal clock signal PCLKD by multiplying the plurality of frequency-division clock signals PCLK0-n; an internal data strobe signal generation circuit 400 that generates an internal data strobe signal IDQS by adding the amount of delay of the multiplier circuit 200 to an external data strobe signal DQS; and a skew detection circuit 500 that measures a skew between the internal clock signal PCLKD and the internal data strobe signal IDQS. Thus, the characteristics of the internal data strobe signal generation circuit 400 and the characteristics of the multiplier circuit 200 are substantially matched, thereby allowing an accurate write leveling operation.

Abstract translation: 要解决的问题：执行准确的写入调平操作。 解决方案：半导体器件包括例如：分频器电路100，其通过对外部时钟信号CK进行分频而产生具有彼此不同相位的多个分频时钟信号PCLK0-n; 乘法器电路200，通过将多个分频时钟信号PCLK0-n相乘来产生内部时钟信号PCLKD; 内部数据选通信号生成电路400，通过将乘法电路200的延迟量与外部数据选通信号DQS相加，生成内部数据选通信号IDQS; 以及偏差检测电路500，其测量内部时钟信号PCLKD与内部数据选通信号IDQS之间的偏差。 因此，内部数据选通信号生成电路400的特性和乘法器电路200的特性基本匹配，从而允许精确的写入调平操作。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2013020678A

公开(公告)日：2013-01-31

申请号：JP2011154402

申请日：2011-07-13

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： KAIWA O ,  MATSUI YOSHINORI

IPC: G11C11/401 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/108

CPC classification number: G06F13/40 ,  G06F13/4059

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory device that enables high-speed input-output operation by controlling a maximum value of delay between a memory cell array and an input-output buffer.SOLUTION: A semiconductor memory device comprises: a memory cell array part where multiple memory cell arrays are arranged; a peripheral circuit part where an external input-output circuit is arranged; and an internal bus 4 that connects the multiple memory cell arrays with the peripheral circuit part. The peripheral circuit part comprises: multiple external input-output buffers 23; and multiple bus interface circuits 24 that mutually convert, between them and the memory cell arrays, data for inputting and outputting the internal bus in parallel and data for inputting and outputting the multiple external input-output buffers in series. The multiple bus interface circuits 24 are arranged collectively between the internal bus 4 and the multiple external input-output buffers so that a distance d1 between the multiple bus interface circuits becomes smaller than a distance d2 between the multiple external input-output buffers and also than a maximum value d3 of a wiring width of the internal bus.

Abstract translation: 要解决的问题：提供一种通过控制存储单元阵列和输入 - 输出缓冲器之间的最大延迟值来实现高速输入输出操作的半导体存储器件。 解决方案：半导体存储器件包括：存储单元阵列部分，其中布置有多个存储单元阵列; 设置外部输入输出电路的外围电路部分; 以及将多个存储单元阵列与外围电路部分连接的内部总线4。 外围电路部分包括：多个外部输入 - 输出缓冲器23; 以及在它们和存储单元阵列之间相互转换用于并行输入和输出内部总线的数据的多总线接口电路24以及用于串行输入和输出多个外部输入 - 输出缓冲器的数据。 多总线接口电路24集中布置在内部总线4和多个外部输入 - 输出缓冲器之间，使得多个总线接口电路之间的距离d1变得小于多个外部输入 - 输出缓冲器之间的距离d2，并且也比 内部总线的布线宽度的最大值d3。 版权所有（C）2013，JPO＆INPIT