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公开(公告)号：DE10107427B4
公开(公告)日：2007-06-14
申请号：DE10107427
申请日：2001-02-16
Applicant: ELPIDA MEMORY INC
Inventor： MATSUI YOSHINORI , IKEDA HIROAKI
Abstract: A semiconductor memory device, that uses redundant memory cell clusters sharing one data transfer bus line to perform defect recovery for a plurality of defects, and provides an improved rate of recovery. The semiconductor memory device is formed from a main memory, a sub-memory functioning as cache memory, and a plurality of data transfer bus lines, which are configured so that data can be transferred bi-directionally between said main memory and said sub-memory; and performs defect recovery for defects located in said main memory based on an address signal (sub-memory column selecting signal SYm) for said sub-memory and address signals (main memory row selecting signal DXn and bank selecting signal BS) in said main memory, which correspond to said address.
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公开(公告)号：DE10238577A1
公开(公告)日：2003-04-24
申请号：DE10238577
申请日：2002-08-22
Applicant: ELPIDA MEMORY INC
Inventor： MATSUI YOSHINORI
IPC: G11C11/409 , G06F3/00 , G06F12/00 , G06F13/16 , G11C7/10 , G11C11/401 , G11C11/4063 , G11C11/407 , H03K19/0175 , G06F13/00
Abstract: In a memory device which is used with the memory device connected to a data bus, the memory device includes an active termination circuit for terminating the memory device when the active termination circuit is electrically put into an active state and for unterminating the memory device when the active termination circuit is electrically put into an inactive state. The memory device further includes a control circuit for controlling the active termination circuit to electrically put the active termination circuit into the active state or the inactive state.
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公开(公告)号：DE102004020038A1
公开(公告)日：2004-12-09
申请号：DE102004020038
申请日：2004-04-21
Applicant: ELPIDA MEMORY INC
Inventor： MATSUI YOSHINORI , SUGANO TOSHIO , IKEDA HIROAKI
IPC: G06F12/00 , G06F13/16 , G11C5/00 , G11C5/02 , G11C5/06 , G11C7/00 , G11C7/10 , H01L25/00 , H01L25/065 , H01L25/07 , H01L25/18
Abstract: The dynamic RAM (DRAM) module comprises several DRAM chips (201) stacked on input-output chip (211), connected through penetration electrodes (215). An independent claim is also included for a memory system.
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公开(公告)号：DE10124112B4
公开(公告)日：2008-12-18
申请号：DE10124112
申请日：2001-05-17
Applicant: ELPIDA MEMORY INC
Inventor： MATSUI YOSHINORI , YAMAKOSHI HIROYUKI
IPC: G11C11/407 , G11C8/08 , G11C8/12 , G11C11/401 , G11C29/00 , G11C29/18
Abstract: A semiconductor memory includes a block selection circuit, a redundancy main word decoder, a word reset circuit, and a word driver circuit. The block selection circuit outputs a block selection signal based on an address signal. The redundancy main word decoder generates a redundancy main word signal in response to the block selection signal. The word reset circuit outputs a word reset signal in response to the redundancy main word signal. The word driver circuit drives one of word lines in response to the word reset signal, a main word signal indicating selection of the word driver circuit, and a word decode signal indicating selection of the one of word lines.
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公开(公告)号：DE102004020038B4
公开(公告)日：2008-12-18
申请号：DE102004020038
申请日：2004-04-21
Applicant: ELPIDA MEMORY INC
Inventor： MATSUI YOSHINORI , SUGANO TOSHIO , IKEDA HIROAKI
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Patent Agency Ranking
公开(公告)号：DE10326925A1
公开(公告)日：2005-06-16
申请号：DE10326925
申请日：2003-06-13
Applicant: ELPIDA MEMORY INC
Inventor： MATSUI YOSHINORI
IPC: G06F13/16 , G06F12/00 , G11C7/10 , G11C7/22 , G11C11/406 , G11C7/00 , G11C11/4063
Abstract: A memory system and a control method for the same enable stable operation at high frequencies without a radiant noise problem. In the memory system, a plurality of DRAMs is provided on each of a plurality of modules, and each DRAM is connected with a memory controller by data lines and clock lines. The clock lines have a topology exclusively applied to each module, while the data lines have a topology for connecting them to their associated DRAMs on each module. Command/address lines also have a topology similar to that of the clock lines. In this case, data signals supplied through the data lines and clock and command/address signals supplied through the clock lines and the command/address lines are transferred at different timings between the DRAMs and the memory controller. For this reason, the DRAMs and the memory controller are provided with circuits for matching the timings.
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公开(公告)号：DE10235448A1
公开(公告)日：2003-06-05
申请号：DE10235448
申请日：2002-08-02
Applicant: ELPIDA MEMORY INC
Inventor： MATSUI YOSHINORI
IPC: G06F12/00 , G06F1/10 , G11C7/22 , G11C11/4076 , G11C29/50 , G11C11/407 , G11C7/00
Abstract: In a memory system having a memory controller 20 and at least one DRAM 30 , the memory controller 20 receives a continuous and alternate inversion signal as a pseudo clock signal from the DRAM 30 , and generates an internal reception clock signal for a DQ signal on the basis of the continuous and alternate inversion signal and a base clock signal. Then, the memory controller 20 counts the number of the receiving internal clocks from the moment an OUT1 command is issued to the DRAM 30 until a high-level data signal is received as the DQ data signal from the DRAM 30 , and retains the count result as the number of delay clocks. Thus, the memory controller 20 can receive read data (DQ signal) on the basis of the internal reception clock signal when time equivalent to the number of the delay clocks passes after the read command is issued.
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公开(公告)号：DE10235448B4
公开(公告)日：2011-07-28
申请号：DE10235448
申请日：2002-08-02
Applicant: ELPIDA MEMORY INC
Inventor： MATSUI YOSHINORI
IPC: G06F12/00 , G11C7/00 , G06F1/10 , G06F13/40 , G11C7/22 , G11C11/407 , G11C11/4076 , G11C29/50 , H04L7/00
Abstract: Eichverfahren zur Verwendung in einem Speichersystem mit einer Speichersteuerung (20) und einer Halbleiterspeichervorrichtung (30) zum Durchführen einer Signalübertragung zwischen der Halbleiterspeichervorrichtung (30) und der Speichersteuerung (20) in Übereinstimmung mit einem Referenztaktsignal und zum angepassten Empfangen eines DQ-Signals von der Halbleiterspeichervorrichtung (30) durch die Speichersteuerung (20), mit: einem ersten Schritt, Übertragen eines kontinuierlichen und alternierenden Inversionssignals als einem initialisierenden DQ-Signal an einen DQ-Bus (102) von der Halbleiterspeichervorrichtung (30) in Übereinstimmung mit dem Referenztaktsignal, das von der Halbleiterspeichervorrichtung (30) empfangen wurde; und einem zweiten Schritt, Erzeugen eines internen Empfangstaktsignals in der Speichersteuerung (20) in Antwort auf das initialisierende DQ-Signal, wobei eine Phasendifferenz zwischen dem initialisierenden DQ-Signal, das von der Speichersteuerung (20) empfangen worden ist, und dem Referenztaktsignal, das von der Speichersteuerung (20) übertragen wurde, gehalten wird, wobei die Speichersteuerung (20) das DQ-Signal von der Halbleiterspeichervorrichtung (30) auf der Basis des internen Empfangstaktsignals empfängt.
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公开(公告)号：JP2009009665A
公开(公告)日：2009-01-15
申请号：JP2007171979
申请日：2007-06-29
Applicant: Elpida Memory Inc , エルピーダメモリ株式会社
Inventor： TOHO YOSHIROU , OISHI HAYATO , HARAGUCHI YOSHINORI , MATSUI YOSHINORI
IPC: G11C11/4096 , G11C11/4091 , G11C11/4093
CPC classification number: G11C7/1048 , G11C7/1051 , G11C7/1069
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor storage device which improves precharge speed of data IO lines and data amplifiers without increasing current consumption to increase speed in reading and writing data from and into memory.
SOLUTION: The semiconductor storage device comprises a column decoder for generating a column selection signal to select any of a plurality of bit lines connected to the memory cells corresponding to inputted column address, a bit line selection switch for connecting any of a plurality of the bit line pairs with data IO line pairs to output the data read from the memory cell to the outside by the column selection signal, a data amplifier for amplifying a difference between the data IO line pairs to output the read data to an output buffer, a data IO switch provided for the data IO line, an IO precharge circuit for precharging the data IO line pair except for the data amplifier, and an amplifier precharge circuit for precharging the IO line pair of the data amp.
COPYRIGHT: (C)2009,JPO&INPITAbstract translation: 要解决的问题：提供一种提高数据IO线和数据放大器的预充电速度的半导体存储装置，而不增加电流消耗，从而提高从存储器读取数据的速度。 解决方案：半导体存储装置包括列解码器，用于产生列选择信号，以选择与输入的列地址相对应的与存储单元连接的多个位线中的任何一个位线;位线选择开关，用于连接多个 与数据IO线对的位线对，通过列选择信号将从存储器单元读取的数据输出到外部;数据放大器，用于放大数据IO线对之间的差异，以将读取的数据输出到输出缓冲器 为数据IO线提供的数据IO开关，用于对数据放大器以外的数据IO线对进行预充电的IO预充电电路和用于对数据放大器的IO线对进行预充电的放大器预充电电路。 版权所有（C）2009，JPO＆INPIT
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公开(公告)号：JP2008299925A
公开(公告)日：2008-12-11
申请号：JP2007143142
申请日：2007-05-30
Applicant: Elpida Memory Inc , エルピーダメモリ株式会社
Inventor： MATSUI YOSHINORI
IPC: G11C29/02 , G11C11/401 , G11C11/407 , G11C29/04
CPC classification number: G11C29/48 , G11C29/1201 , G11C2029/5006
Abstract: PROBLEM TO BE SOLVED: To reduce the pitch of data input/output PADs of a semiconductor memory without raising the required positioning precision for probe inspection.
SOLUTION: This memory has a memory cell array 101 composed of memory cells, signal terminals DQ1-DQn arranged with a small pitch, and test signal terminals TEST 1-4 arranged with a large pitch, and selects the data to write in the memory cells from either the data inputted through the signal terminals or the data inputted through the test signal terminals. A data latch circuit 405 is also provided to allocate the data in duplicate based on the arrangement of the signal terminals.
COPYRIGHT: (C)2009,JPO&INPITAbstract translation: 要解决的问题：为了降低半导体存储器的数据输入/输出PAD的间距，而不增加探针检查所需的定位精度。 解决方案：该存储器具有由存储单元，以小间距排列的信号端子DQ1-DQn和以大间距排列的测试信号端子TEST 1-4构成的存储单元阵列101，并选择要写入的数据 来自通过信号端子输入的数据的存储器单元或通过测试信号端子输入的数据。 还提供数据锁存电路405，以便根据信号终端的配置分配一式两份的数据。 版权所有（C）2009，JPO＆INPIT
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