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公开(公告)号：US11068394B2
公开(公告)日：2021-07-20
申请号：US16567241
申请日：2019-09-11
Inventor： Jeongmin Yang , Young-Su Kwon
Abstract: Provided is a neural network system for processing data transferred from an external memory. The neural network system includes an internal memory storing input data transferred from the external memory, an operator performing a multidimensional matrix operation by using the input data of the internal memory and transferring a result of the multidimensional array operation as output data to the internal memory, and a data moving controller controlling an exchange of the input data or the output data between the external memory and the internal memory. The data moving controller reorders a dimension order with respect to an access address of the external memory to generate an access address of the internal memory, for the multidimensional matrix operation.
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公开(公告)号：US20180157549A1
公开(公告)日：2018-06-07
申请号：US15832862
申请日：2017-12-06
Inventor： Jin Ho Han , Young-Su Kwon
IPC: G06F11/07 , G06F12/0815 , G06F12/0804
CPC classification number: G06F11/079 , G06F11/0724 , G06F11/0751 , G06F11/1641 , G06F11/1675 , G06F12/0804 , G06F12/0815 , G06F12/0868 , G06F2212/1048 , G06F2212/60 , G06F2212/621
Abstract: A multi-core processor connected to main memory or peripheral device and having dual modular redundancy mode in which each processor performs the same task includes a first processor which generates first write-in data by performing the task, and writes the first write-in data to the main memory or peripheral device after fault detection operation on the first write-in data, a second processor which generates second write-in data by performing the task, and prevents writing of the second write-in data to the main memory or peripheral device after the fault detection operation on the second write-in data, and a fault manager which performs the fault detection operation by comparing the first write-in data with the second write-in data in the mode, wherein the first write-in data is written to the main memory using first data cache, which is managed using dirty bit indicating whether to synchronize with the main memory.
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公开(公告)号：US09859889B2
公开(公告)日：2018-01-02
申请号：US15414236
申请日：2017-01-24
Inventor： Woojoo Lee , Young-Su Kwon , Kyung Jin Byun , Jin Ho Han , Nak Woong Eum
CPC classification number: H03K19/0013 , G06F3/0202 , H01L27/1104 , H01L29/49 , H03K17/9638 , H03K19/00369 , H03K19/0944
Abstract: An Ultra Low Voltage (ULV) digital circuit includes a logic circuit comprising a plurality of logic gates and a plurality of buffered interconnects for connecting between the plurality of logic gates, a temperature sensor configured to detect a temperature of the logic circuit, and a voltage controller configured to control a driving voltage provided to the logic circuit in order to reduce a power consumption of the logic circuit based on the detected temperature. Each of the plurality of logic gates and buffered interconnects reduces a signal delay as a temperature increases.
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公开(公告)号：US12113887B2
公开(公告)日：2024-10-08
申请号：US17881417
申请日：2022-08-04
Inventor： Seon-Ho Han , Young-Su Kwon
CPC classification number: H04L7/033 , H03L7/0807 , H03L7/093
Abstract: Disclosed are a digital CDR circuit and a feedback loop circuit including the same. The digital CDR circuit includes a phase detector that receives an input signal and outputs a phase detection result signal corresponding to a determination result for a sampling time based on the input signal, a charge pump that receives the phase detection result signal and outputs an amplified signal obtained by multiplying the phase detection result signal by a gain, a loop filter that receives the amplified signal and filters the amplified signal to output a filtered signal, and a phase shift control code generator that generates a control signal for controlling a phase of a signal based on the filtered signal, and the input signal includes plural data signals and plural error signals, and the data signals and the error signals are digital signals which are quantized based on a signal magnitude.
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公开(公告)号：US11146253B1
公开(公告)日：2021-10-12
申请号：US17105817
申请日：2020-11-27
Inventor： Young-deuk Jeon , Young-Su Kwon , Seong Min Kim , In San Jeon , Min-Hyung Cho , Jin Ho Han
IPC: H03K3/00 , H03K3/3565 , H03K19/0185 , H03K19/00 , H03K5/08 , G11C11/413 , G01R19/165
Abstract: Disclosed is a receiving circuit, which includes a hysteresis detector that receives an input signal corresponding to a first voltage level and outputs a detection signal having a first threshold voltage and a second threshold voltage, and a level shifter that receives the detection signal, converts the first voltage level of the detection signal to a second voltage level higher than the first voltage level so as to be output as an output signal, and outputs a feedback signal of the second voltage level, and the hysteresis detector receives the feedback signal from the level shifter and adjusts the first threshold voltage and the second threshold voltage based on the feedback signal.
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Patent Agency Ranking
26.发明授权公开(公告)号：US11025840B2
公开(公告)日：2021-06-01
申请号：US16356788
申请日：2019-03-18
Inventor： Hyun Kyu Yu , Sung Weon Kang , Young-Su Kwon , Joo Hyun Lee
Abstract: Provided is an image sensor. The image sensor includes a pixel array including pixels arranged along a first direction and a second direction, and partitioned into blocks, a converter configured to convert image signals outputted from the pixels into digital signals based on an image, and an image signal processor configured to add amplitudes of the digital signals belonging to each of the blocks to determine edge blocks among the blocks, compare the amplitudes of the digital signals to determine directions in which direction lines of the edge blocks are directed, and connect the direction lines to extract an edge of the image.
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公开(公告)号：US10180904B2
公开(公告)日：2019-01-15
申请号：US15241902
申请日：2016-08-19
Inventor： Jin Ho Han , Young-Su Kwon , Kyung Jin Byun , Nak Woong Eum
IPC: G06F12/08 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0875
Abstract: Provided is a cache memory. The cache memory includes a first to Nth level-1 caches configured to correspond to first to Nth cores, respectively, a level-2 sharing cache configured to be shared by the first to Nth level-1 caches, and a coherence controller configured to receive an address from each of the first to Nth cores and allocate at least a partial area in an area of the level-2 sharing cache to one of the first to Nth level-1 caches based on the received address.
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公开(公告)号：US10013310B2
公开(公告)日：2018-07-03
申请号：US15241808
申请日：2016-08-19
Inventor： Jin Ho Han , Young-Su Kwon , Kyoung Seon Shin , Kyung Jin Byun , Nak Woong Eum
IPC: G06F11/10 , G06F12/08 , G06F12/0804 , G06F12/0895
CPC classification number: G06F11/1076 , G06F11/1044 , G06F12/0804 , G06F12/0808 , G06F12/0864 , G06F12/0895 , G06F12/0897 , G06F2212/1032 , Y02D10/13
Abstract: Provided is an operating method of a cache memory device includes receiving an address from an external device, reading an entry corresponding to at least a portion of the received address among a plurality of entries that are included in the cache memory, performing error detection on additional information that is included in the read entry, and performing a recovery operation on the entry based on a result of error detection and the additional information. The entry includes the additional information and a cache line corresponding to the additional information, and the additional information includes a tag, valid bit, and dirty bit that correspond to the cache line.
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公开(公告)号：US09830218B2
公开(公告)日：2017-11-28
申请号：US14858448
申请日：2015-09-18
Inventor： Jin-Ho Han , Young-Su Kwon
IPC: G06F11/10 , G06F12/0895
CPC classification number: G06F11/1064 , G06F12/0895 , G06F2212/1032
Abstract: The exemplary embodiments of the invention relates to fault tolerance of a cache memory which recovers an error occurred in the cache memory or reports an error. A cache memory may include a first layer cache configured to store data requested from a processor, together with a tag related to the data and parity check bits for detecting data error and tag error; a second layer cache configured to store data requested from the first layer cache, together with parity check bits and an error correction code(ECC) bit for detecting data error and tag error; and a fault tolerance unit configured to generate an error signal indicating whether the data error or tag error occurred in at least one of the first layer cache and the second layer cache is recoverable.
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公开(公告)号：US09575852B2
公开(公告)日：2017-02-21
申请号：US14749558
申请日：2015-06-24
Inventor： Young-Su Kwon
CPC classification number: G06F11/1641 , G06F11/1438 , G06F11/165 , G06F11/1658 , G06F11/1695 , G06F11/183
Abstract: Exemplary embodiments of the present invention relate to a failure recovery apparatus of digital logic circuit and method thereof when a fault occurs in the digital logic circuit. A failure recovery apparatus according to an embodiment of the present invention comprises: a fault detection block configured to determine fault occurrence by comparing output results of a plurality of digital logic circuit which perform the same operation using a clock having a first cycle; and a failure recovery block configured to perform a failure recovery operation of the plurality of digital logic circuit by using a clock having a second cycle which is longer than the first cycle when it is determined as that a fault occurs. According to exemplary embodiments of the present invention, when a fault occurs in digital logic circuits due to external factors, it provides high reliability in failure recovery of the digital logic circuits.
Abstract translation: 本发明的示例性实施例涉及数字逻辑电路的故障恢复装置及其在数字逻辑电路中发生故障时的方法。 根据本发明实施例的故障恢复装置包括：故障检测块，被配置为通过比较使用具有第一周期的时钟执行相同操作的多个数字逻辑电路的输出结果来确定故障发生; 以及故障恢复块，被配置为当确定为故障发生时，通过使用具有比所述第一周期长的第二周期的时钟来执行所述多个数字逻辑电路的故障恢复操作。 根据本发明的示例性实施例，当由于外部因素在数字逻辑电路中发生故障时，其在数字逻辑电路的故障恢复中提供高可靠性。
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