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    Sensing circuit for recognizing movement and movement recognizing method thereof
    1.
    发明授权
    Sensing circuit for recognizing movement and movement recognizing method thereof 有权
    用于识别其运动和运动识别方法的感测电路

    公开(公告)号：US09341713B2

    公开(公告)日：2016-05-17

    申请号：US14454603

    申请日：2014-08-07

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Chun-Gi Lyuh ,  Jung Hee Suk ,  Young-deuk Jeon ,  Tae Moon Roh

    IPC: G01S17/58 ,  G01S17/00 ,  G01S7/491

    CPC classification number: G01S17/58 ,  G01S7/4912 ,  G01S17/003

    Abstract: Provided is a sensing circuit for recognizing a movement including: at least one light emitting device outputting light; at least one light receiving device receiving the light reflected by an object on the light emitting device and generating a plurality of current signals proportional to an amount of incident light; a signal conversion unit converting the plurality of current signals into a plurality of digital signals; a recognition unit measuring a synthetic digital signal to determine whether an object moves by receiving the plurality of current signals; and a control unit controlling the recognition unit, wherein the recognition unit generates a clock signal for the synthetic digital signal greater than a critical value and measures a count generated by the clock signal; and the control unit determines whether the object moves through a comparison of the count and a reference value.

    Abstract translation: 提供一种用于识别移动的感测电路，包括：至少一个输出光的发光装置; 至少一个光接收装置，其接收由所述发光装置上的物体反射的光，并产生与入射光量成比例的多个电流信号; 信号转换单元，将所述多个电流信号转换成多个数字信号; 识别单元，测量合成数字信号，以通过接收多个电流信号来确定对象是否移动; 以及控制单元，其控制所述识别单元，其中所述识别单元生成大于临界值的所述合成数字信号的时钟信号，并测量由所述时钟信号产生的计数; 并且控制单元确定对象是否通过计数和参考值的比较来移动。

    Neuromorphic arithmetic device and operating method thereof
    2.
    发明授权
    Neuromorphic arithmetic device and operating method thereof 有权

    公开(公告)号：US11204740B2

    公开(公告)日：2021-12-21

    申请号：US16695509

    申请日：2019-11-26

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Min-Hyung Cho ,  Young-deuk Jeon ,  Ki Hyuk Park ,  Joo Hyun Lee

    IPC: G06F7/544 ,  G06N3/063

    Abstract: The neuromorphic arithmetic device performs a multiply-accumulate (MAC) calculation using a multiplier and an accumulator. The neuromorphic arithmetic device includes an offset accumulator configured to receive a plurality of offset data measured a plurality of times and accumulate the plurality of offset data, a bit extractor configured to obtain average offset data by extracting at least one first bit from the plurality of accumulated offset data, and a cumulative synapse array configured to accumulate a plurality of multiplication values generated by the multiplier and output a cumulative result of the plurality of multiplication values corrected according to the average offset data.

    SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND METHOD OF OPERATING BUILT-IN SELF-TEST DEVICE FOR TESTING THE CONVERTER
    6.
    发明申请
    SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND METHOD OF OPERATING BUILT-IN SELF-TEST DEVICE FOR TESTING THE CONVERTER 有权
    成功的近似寄存器模拟数字转换器和操作内置自检器件的测试转换器的方法

    公开(公告)号：US20150029048A1

    公开(公告)日：2015-01-29

    申请号：US14178187

    申请日：2014-02-11

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Young-deuk Jeon

    IPC: H03M1/10 ,  H03M1/12

    CPC classification number: H03M1/1071 ,  H03M1/00 ,  H03M1/0682 ,  H03M1/1023 ,  H03M1/468

    Abstract: Provided is a successive approximation register analog-to-digital converter (SAR ADC) including a digital-to-analog converter (DAC) generating and outputting first and second level voltages based on first and second analog input signals and a reference voltage signal; a comparator comparing the first and second level voltages and outputting a comparison signal according to a comparison result; and an SAR logic generating a digital signal based on the comparison signal, wherein the DAC includes: first and second input switches controlling reception of the first and second analog input signals, respectively; a first discharge switch connected electrically to the first input switch, the first discharge switch discharging leakage current according to an operation of the first input switch; and a second discharge switch connected electrically to the second input switch, the second discharge switch discharging leakage current according to an operation of the second input switch.

    Abstract translation: 提供了包括基于第一和第二模拟输入信号和参考电压信号产生并输出第一和第二电平电压的数模转换器（DAC）的逐次逼近寄存器模拟 - 数字转换器（SAR ADC） 比较器，比较第一和第二电平电压，并根据比较结果输出比较信号; 以及基于所述比较信号产生数字信号的SAR逻辑，其中所述DAC包括：分别控制所述第一和第二模拟输入信号的接收的第一和第二输入开关; 与第一输入开关电连接的第一放电开关，第一放电开关根据第一输入开关的操作放电泄漏电流; 以及与第二输入开关电连接的第二放电开关，第二放电开关根据第二输入开关的操作来放电泄漏电流。

    Successive approximation register analog-to-digital converter and method of operating built-in self-test device for testing the converter
    7.
    发明授权
    Successive approximation register analog-to-digital converter and method of operating built-in self-test device for testing the converter 有权
    逐次逼近寄存器模数转换器和操作内置自检器件的测试方法

    公开(公告)号：US08933830B1

    公开(公告)日：2015-01-13

    申请号：US14178187

    申请日：2014-02-11

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Young-deuk Jeon

    IPC: H03M1/00 ,  H03M1/10 ,  H03M1/12

    CPC classification number: H03M1/1071 ,  H03M1/00 ,  H03M1/0682 ,  H03M1/1023 ,  H03M1/468

    Abstract: Provided is a successive approximation register analog-to-digital converter (SAR ADC) including a digital-to-analog converter (DAC) generating and outputting first and second level voltages based on first and second analog input signals and a reference voltage signal; a comparator comparing the first and second level voltages and outputting a comparison signal according to a comparison result; and an SAR logic generating a digital signal based on the comparison signal, wherein the DAC includes: first and second input switches controlling reception of the first and second analog input signals, respectively; a first discharge switch connected electrically to the first input switch, the first discharge switch discharging leakage current according to an operation of the first input switch; and a second discharge switch connected electrically to the second input switch, the second discharge switch discharging leakage current according to an operation of the second input switch.

    Abstract translation: 提供了包括基于第一和第二模拟输入信号和参考电压信号产生并输出第一和第二电平电压的数模转换器（DAC）的逐次逼近寄存器模拟 - 数字转换器（SAR ADC） 比较器，比较第一和第二电平电压，并根据比较结果输出比较信号; 以及基于所述比较信号产生数字信号的SAR逻辑，其中所述DAC包括：分别控制所述第一和第二模拟输入信号的接收的第一和第二输入开关; 与第一输入开关电连接的第一放电开关，第一放电开关根据第一输入开关的操作放电泄漏电流; 以及与第二输入开关电连接的第二放电开关，第二放电开关根据第二输入开关的操作来放电泄漏电流。

    Neuromorphic arithmetic device and operating method thereof
    10.
    发明授权
    Neuromorphic arithmetic device and operating method thereof 有权

    公开(公告)号：US11494630B2

    公开(公告)日：2022-11-08

    申请号：US16742808

    申请日：2020-01-14

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Young-deuk Jeon ,  Byung Jo Kim ,  Ju-Yeob Kim ,  Jin Kyu Kim ,  Ki Hyuk Park ,  Mi Young Lee ,  Joo Hyun Lee ,  Min-Hyung Cho

    IPC: G06N3/063 ,  G06F7/575 ,  G06F17/15

    Abstract: The neuromorphic arithmetic device comprises an input monitoring circuit that outputs a monitoring result by monitoring that first bits of at least one first digit of a plurality of feature data and a plurality of weight data are all zeros, a partial sum data generator that skips an arithmetic operation that generates a first partial sum data corresponding to the first bits of a plurality of partial sum data in response to the monitoring result while performing the arithmetic operation of generating the plurality of partial sum data, based on the plurality of feature data and the plurality of weight data, and a shift adder that generates the first partial sum data with a zero value and result data, based on second partial sum data except for the first partial sum data among the plurality of partial sum data and the first partial sum data generated with the zero value.

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