公开(公告)号：US20230420448A1

公开(公告)日：2023-12-28

申请号：US17808364

申请日：2022-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Souvick Mitra ,  Alain F. Loiseau ,  Robert J. Gauthier, JR. ,  Meng Miao ,  Anindya Nath ,  Wei Liang

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/7436

Abstract: A structure includes trigger control circuitry for an SCR including: a first transistor having two P-type semiconductor terminals connected to an Nwell and a Pwell of the SCR; a second transistor having two N-type semiconductor terminals connected to the Pwell and ground; and, optionally, an additional transistor having two P-type semiconductor terminals connected to the Nwell and ground. Control terminals of the transistors receive the same control signal (e.g., RST from a power-on-reset). When a circuit connected to the SCR for ESD protection is powered on, ESD risk is limited so RST switches to high. Thus, the first transistor and optional additional transistor turn off and the second transistor turns on, reducing leakage. When the circuit is powered down, the ESD risk increases so RST switches to low. Thus, the first transistor and optional additional transistor turn on and the second transistor turns off, lowering the trigger voltage and current.

公开(公告)号：US20230402447A1

公开(公告)日：2023-12-14

申请号：US17806797

申请日：2022-06-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Alain F. Loiseau ,  Rajendran Krishnasamy ,  Souvick Mitra

IPC: H01L27/02 ,  H01L29/87

CPC classification number: H01L27/0248 ,  H01L29/87

Abstract: Disclosed are a structure and method. The structure includes a substrate having monocrystalline lower and upper portions and a high resistance portion (e.g., a trap-rich amorphous portion) between the lower and upper portions. An isolation region extends through the upper portion, is above the high resistance portion, and is positioned laterally adjacent to a device section of the upper portion also above the high resistance portion. One or more devices (e.g., a diode, multiple diodes, a diode string, multiple diode strings, etc.) are on the trench isolation region, on the device section, and/or within the device section. The device(s) are separated from the lower portion by the high resistance portion and, potentially, by the isolation region or the device section. Such device(s) can be employed for electrostatic discharge (ESD) protection on RFIC chips and can sustain a larger RF voltage, provide area savings, reduce parasitic capacitance, improve harmonics, etc.

公开(公告)号：US20230395714A1

公开(公告)日：2023-12-07

申请号：US17831496

申请日：2022-06-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Alain Loiseau ,  Rajendran Krishnasamy

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7835 ,  H01L21/823892 ,  H01L29/66659

Abstract: Device structures with an isolation well and methods of forming a device structure with an isolation well. The structure comprises a first well of a first conductivity type in a semiconductor substrate, and a second well of a second conductivity type in the semiconductor substrate. The second conductivity type is opposite to the first conductivity type. The first well includes a plurality of segments, and the second well is positioned in a vertical direction between the segments of the first well and a top surface of the semiconductor substrate.

公开(公告)号：US20250159999A1

公开(公告)日：2025-05-15

申请号：US18388441

申请日：2023-11-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Uppili S. Raghunathan ,  Rajendran Krishnasamy ,  Sagar Premnath Karalkar ,  Alexander M. Derrickson ,  Vibhor Jain

IPC: H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a silicon control rectifier (SCR) and methods of manufacture. The structure includes: a doped region in a semiconductor substrate; at least two regions of semiconductor material comprising opposite doping types over the doped region; and polysilicon regions over respective ones of the least two regions of semiconductor material.

公开(公告)号：US12205943B2

公开(公告)日：2025-01-21

申请号：US17890725

申请日：2022-08-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Alain F. Loiseau ,  Souvick Mitra ,  Rajendran Krishnasamy

IPC: H01L27/02 ,  H01L29/73 ,  H01L29/735 ,  H01L29/739

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a diode over a lateral bipolar transistor. A structure according to the disclosure may include a lateral bipolar transistor within a monocrystalline semiconductor over a substrate. An insulator layer is over a portion of the monocrystalline semiconductor. A diode is within a polycrystalline semiconductor on the insulator layer. A cathode of the diode is coupled to a first well within the monocrystalline semiconductor. The first well defines one of an emitter terminal and a collector terminal of the lateral bipolar transistor.

公开(公告)号：US12125842B2

公开(公告)日：2024-10-22

申请号：US17831545

申请日：2022-06-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anindya Nath ,  Souvick Mitra

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/66371 ,  H01L29/7412

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked diode-trigger silicon controlled rectifiers and methods of manufacture. The structure includes: a silicon controlled rectifier in a trap rich region of a semiconductor substrate; and at least one diode built in polysilicon (gate material) and isolated by a gate-dielectric.

公开(公告)号：US20240266422A1

公开(公告)日：2024-08-08

申请号：US18166041

申请日：2023-02-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Satyasuresh Vvss Choppalli ,  Rajendran Krishnasamy ,  Robert J. Gauthier, JR. ,  Anindya Nath

IPC: H01L29/745

CPC classification number: H01L29/7455

Abstract: Disclosed structures include a semiconductor controlled rectifier or bi-directional semiconductor controlled rectifier with a trigger voltage (Vtrig) that is tunable. Some structures include a semiconductor controlled rectifier with an Nwell and Pwell in a semiconductor layer, with a P-type diffusion region in the Nwell, and with an N-type diffusion region in the Pwell. Gate(s) on the well(s) are separated from the junction between the wells and from the diffusion regions. Other structures include a bidirectional semiconductor controlled rectifier with a Pwell between first and second Nwells in a semiconductor layer, with first P-type and N-type diffusion regions in the first Nwell, and with second P-type and N-type diffusion regions in the second Nwell. Gate(s) on the well(s) are separated from junctions between the Nwells and the Pwell and from any diffusion regions. In these structures, the gate(s) can be left floating or biased to tune Vtrig using gate leakage current.

公开(公告)号：US11935946B2

公开(公告)日：2024-03-19

申请号：US17849867

申请日：2022-06-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Souvick Mitra ,  Anindya Nath

IPC: H01L29/745 ,  H01L29/66

CPC classification number: H01L29/7455 ,  H01L29/66363

Abstract: Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure comprises a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a first well and a second well in the semiconductor substrate beneath the dielectric layer. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the second well adjoins the first well along a p-n junction. The structure further comprises a first terminal and a second terminal above the dielectric layer, a first connection extending through the dielectric layer from the first terminal to the first well, and a second connection extending through the dielectric layer from the second terminal to the second well.

公开(公告)号：US20230395590A1

公开(公告)日：2023-12-07

申请号：US17805697

申请日：2022-06-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Rajendran Krishnasamy ,  Robert J. Gauthier, JR.

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: An integrated circuit (IC) structure with a conductive pathway through resistive semiconductor material, e.g., for bipolar transistors, is provided. The IC structure may include a resistive semiconductor material having a first end coupled to a first doped semiconductor material. The first doped semiconductor material has a first doping type. A doped well may be coupled to a second end of the resistive semiconductor material. The doped well has a second doping type opposite the first doping type. A second doped semiconductor material is coupled to the doped well and has the first doping type. The resistive semiconductor material is within a conductive pathway from the first doped semiconductor material to the second doped semiconductor material.

公开(公告)号：US20230197707A1

公开(公告)日：2023-06-22

申请号：US17554222

申请日：2021-12-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Meng Miao ,  Alain Loiseau ,  Souvick Mitra ,  Wei Liang ,  Robert J. Gauthier, JR. ,  Anindya Nath

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/74

CPC classification number: H01L27/0248 ,  H01L27/1207 ,  H01L29/7436

Abstract: Disclosed are embodiments of a semiconductor structure that includes a semiconductor-controlled rectifier (e.g., for electrostatic discharge (ESD) protection). The SCR can be readily integrated into advanced semiconductor-on-insulator processing technology platforms (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform) that employ hybrid semiconductor substrates (i.e., semiconductor substrates with both bulk semiconductor and semiconductor-on-insulator regions) and is configured with an on-Pwell semiconductor-on-insulator gate structure that is tied to an anode terminal to effectively lower the SCR trigger voltage. To further lower the trigger voltage of the SCR, the Pwell on which the gate structure sits may be made narrower than the gate structure and/or the doping profile of the Pwell on which the gate structure sits may be graded (e.g., P to P- closer to insulator layer). Additionally, to minimize parasitic capacitance, the gate structure may be shorter in length than contact regions parallel and adjacent thereto.