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    Anti-tamper x-ray blocking package
    21.
    发明授权
    Anti-tamper x-ray blocking package 有权

    公开(公告)号：US11437329B2

    公开(公告)日：2022-09-06

    申请号：US17070377

    申请日：2020-10-14

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Johnatan A. Kantarovsky ,  Vibhor Jain ,  Siva P. Adusumilli ,  Ajay Raman ,  Sebastian T. Ventrone ,  Yves T. Ngu

    IPC: H01L23/552 ,  H01L23/00 ,  H01L23/522 ,  H01L49/02

    Abstract: The present disclosure relates to integrated circuits, and more particularly, to an anti-tamper x-ray blocking package for secure integrated circuits and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: one or more devices on a front side of a semiconductor material; a plurality of patterned metal layers under the one or more devices, located and structured to protect the one or more devices from an active intrusion; an insulator layer between the plurality of patterned metal layers; and at least one contact providing an electrical connection through the semiconductor material to a front side of the plurality of metals.

    THERMALLY AND ELECTRICALLY CONDUCTIVE INTERCONNECTS
    22.
    发明申请
    THERMALLY AND ELECTRICALLY CONDUCTIVE INTERCONNECTS 有权

    公开(公告)号：US20220189877A1

    公开(公告)日：2022-06-16

    申请号：US17121810

    申请日：2020-12-15

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  John J. Pekarik

    IPC: H01L23/532 ,  H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/373

    Abstract: Processing forms an integrated circuit structure having first and second layers on opposite sides of an insulator, and an interconnect structure extending through the insulator between the first layer and the second layer. The interconnect structure is formed in an opening extending through the insulator between the first layer and the second layer and has an electrical conductor in the opening extending between the first layer and the second layer and a thermally conductive electrical insulator liner along sidewalls of the opening extending between the first layer and the second layer. The electrical conductor is positioned to conduct electrical signals between the first layer and the second layer, and the thermally conductive electrical insulator liner is positioned to transfer heat between the first layer and the second layer.

    Junction field effect transistor (JFET) structure and methods to form same
    24.
    发明授权
    Junction field effect transistor (JFET) structure and methods to form same 有权

    公开(公告)号：US11094834B2

    公开(公告)日：2021-08-17

    申请号：US16790084

    申请日：2020-02-13

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik ,  Judson R. Holt

    IPC: H01L21/00 ,  H01L29/808 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/02 ,  H01L21/225 ,  H01L29/66

    Abstract: A junction field effect transistor (JFET) structure includes a doped polysilicon gate over a channel region of a semiconductor layer. The doped polysilicon gate has a first doping type. A raised epitaxial source is on the source region of the semiconductor layer and adjacent a first sidewall of the doped polysilicon gate, and has a second doping type opposite the first doping type. A raised epitaxial drain is on the drain region of the semiconductor layer and adjacent a second sidewall of the doped polysilicon gate, and has the second doping type. A doped semiconductor region is within the channel region of the semiconductor layer and extending from the source region to the drain region, and a non-conductive portion of the semiconductor layer is within the channel region to separate the doped semiconductor region from the doped polysilicon gate.

    HETEROJUNCTION BIPOLAR TRANSISTORS WITH AIRGAP ISOLATION
    26.
    发明申请
    HETEROJUNCTION BIPOLAR TRANSISTORS WITH AIRGAP ISOLATION 有权

    公开(公告)号：US20210091213A1

    公开(公告)日：2021-03-25

    申请号：US16748055

    申请日：2020-01-21

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Vibhor Jain ,  John J. Pekarik ,  Qizhi Liu ,  Judson Holt

    IPC: H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

    Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A collector layer includes an inclined side surface, and a dielectric layer is positioned in a lateral direction adjacent to the inclined side surface of the collector layer. An intrinsic base is disposed over the collector layer, and an emitter is disposed over the intrinsic base. An airgap is positioned between the dielectric layer and the inclined side surface of the collector layer in the lateral direction, and an extrinsic base is positioned in the lateral direction adjacent to the intrinsic base. The extrinsic base is positioned over the airgap.

    MULTI-SUBSTRATE COUPLING FOR PHOTONIC INTEGRATED CIRCUITS
    28.
    发明申请
    MULTI-SUBSTRATE COUPLING FOR PHOTONIC INTEGRATED CIRCUITS 有权

    公开(公告)号：US20240427095A1

    公开(公告)日：2024-12-26

    申请号：US18338712

    申请日：2023-06-21

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Ravi Prakash Srivastava ,  Yusheng Bian ,  Vibhor Jain

    IPC: G02B6/42

    Abstract: Embodiments of the disclosure provide a multi-substrate coupling for photonic integrated circuits (PICs). Structures of the disclosure may include a first substrate having a first surface. The first surface includes a groove therein. A second substrate has a second surface coupled to the first surface. The second substrate includes a cavity substantially aligned with the groove of the first surface, and a photonic integrated circuit (PIC) structure horizontally distal to the cavity.

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