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45 records (took 0.024 seconds)

    22.
    发明专利
    未知

    公开(公告)号：DE112004002525T5

    公开(公告)日：2006-11-02

    申请号：DE112004002525

    申请日：2004-12-13

    Applicant: IBM

    Inventor： CROMER DARYL CARVIS ,  ELLISON BRANDON JON ,  KERN ERIC RICHARD ,  LOCKER HOWARD JEFFREY

    IPC: H04L12/28 ,  H04W4/02 ,  H04W84/12

    Abstract: A wireless LAN system is provided at its access points with structured data indicating resources, connected and independent (e.g. vending machine) in the connect range of the respective access point. Guest clients, upon connecting, may download "greeting" logic to receive and display the structured data to allow the guest to be quickly at home and productive in an unfamiliar setting.

    BANDWIDTH MANAGEMENT IN A WIRELESS NETWORK
    24.
    发明专利
    BANDWIDTH MANAGEMENT IN A WIRELESS NETWORK 未知

    公开(公告)号：CA2482515A1

    公开(公告)日：2003-11-20

    申请号：CA2482515

    申请日：2003-05-06

    Applicant: IBM

    Inventor： CROMER DARYL CARVIS ,  JAKES PHILIP JOHN ,  LOCKER HOWARD JEFFREY

    IPC: H04W28/02 ,  H04H20/00 ,  H04W24/02 ,  H04W74/00 ,  H04W84/18 ,  H04L12/28 ,  H04L12/56

    Abstract: In accordance with the preferred embodiment, an access point provides dynami c load balancing of network bandwidth between access points within the 802.11 wireless LAN. The access point uses the RTS/CTS protocol to reduce the bandwidth available to a single device using an excessive amount of network bandwidth. The access point places a device that has been monopolizing a network channel on a Restricted List, and regulates bandwidth on the network by not returning a CTS to any client on the Restricted List. When the client 's network usage drops below a policy driven threshold set by the number of network users, the client is removed from the list and the access point will respond to a RTS from the client with a CTS.

    MEMORY CONTROLLER FOR DIRECT OR INTERLEAVE MEMORY ACCESSING
    28.
    发明专利
    MEMORY CONTROLLER FOR DIRECT OR INTERLEAVE MEMORY ACCESSING 未知

    公开(公告)号：AU8345391A

    公开(公告)日：1992-04-09

    申请号：AU8345391

    申请日：1991-08-30

    Applicant: IBM

    Inventor： ALDEREGUIA ALFREDO ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

    IPC: G06F12/06 ,  G11C8/12 ,  G06F13/14

    Abstract: A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank addresses. The decoders produce bank select signals. In direct mode, the decoder outputs are generated according to which bank is addressed. In interleave mode, the two decoder outputs are ANDed to select both banks covering the address range of the selected banks.

    29.
    发明专利
    未知

    公开(公告)号：NO913799L

    公开(公告)日：1992-04-02

    申请号：NO913799

    申请日：1991-09-27

    Applicant: IBM

    Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

    IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G06F13/16

    Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

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