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公开(公告)号：CA1121057A
公开(公告)日：1982-03-30
申请号：CA306954
申请日：1978-07-07
Applicant: IBM
Inventor： CROUSE WILLIAM G
Abstract: NOISE REDUCTION METHOD \A APPARATUS FOR COMPANDED DELTA MODULATORS A noise reduction circuit and method are described for implementation in a delta modulation system for signal transmission. Under certain conditions when the delta modulator has selected the minimum step size for encoding and transmission, the present technique and apparatus are effective to change the minimum step size in a way which prevents low level noise generation from occurring in the delta modulation system. The technique and circuit can be utilized with most commonly available delta modulators which have means for changing the step size (i.e., the delta) but is used to the best effect on more stable implementations of delta modulators where an integrator is replaced by a digital accumulator and a digitalto-analog converter.
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公开(公告)号：CA944076A
公开(公告)日：1974-03-19
申请号：CA145128
申请日：1972-06-20
Applicant: IBM
Inventor： CROUSE WILLIAM G , JONES JOHN E
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公开(公告)号：CA886190A
公开(公告)日：1971-11-16
申请号：CA886190D
Applicant: IBM
Inventor： EPLEY PHILLIP R , CROUSE WILLIAM G
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25.发明专利
公开(公告)号：PL170083B1
公开(公告)日：1996-10-31
申请号：PL30268292
申请日：1992-08-26
Applicant: IBM
Inventor： CARMON DONALD E , CROUSE WILLIAM G , WARE MALCOLM S
IPC: G06F9/50 , G06F13/28 , G06F17/10 , G06F15/163
Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.
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Patent Agency Ranking
公开(公告)号：CA2071333A1
公开(公告)日：1993-03-17
申请号：CA2071333
申请日：1992-06-16
Applicant: IBM
Inventor： CARMON DONALD E , CROUSE WILLIAM G
Abstract: A method and apparatus for controlling the readout rate of information from a sequential storage medium (104), such as a CD-ROM, to maintain synchronism between the device containing the medium and an independent receiver receiving the information. Information is loaded from the media (104) into a buffer (116) at a rate controlled by pulses from a device clock (124). Information is unloaded from the buffer (116) for utilization by the receiver independently of the loading of the buffer. The amount of free space available in the buffer is measured as information is loaded into the buffer. The rate of the clock (122) is dynamically adjusted in response to the amount of free buffer space to maintain the full state of the buffer within predetermined limits. In this manner, the buffer never empties or fills in response to the unloading by the independent receiver.
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