公开(公告)号：AU2475477A

公开(公告)日：1978-11-09

申请号：AU2475477

申请日：1977-05-02

Applicant: IBM

Inventor： DAVIS MICHAEL I ,  MAYES GARY W ,  MCDERMOTT THOMAS S ,  WISE LARRY E

IPC: G06F9/40 ,  G06F9/42 ,  G06F9/16

Abstract: A data processing system is described wherein, during linkage to a subroutine, by a single machine instruction, a complete status save and the assignment of a dynamic work area are effected. By another single machine instruction the process is reversed. The elements of the complete machine status and the dynamic work area are retained in a hardware controlled stack, thus permitting nesting of the subroutine calls.

公开(公告)号：FR2349886A1

公开(公告)日：1977-11-25

申请号：FR7707429

申请日：1977-03-04

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I

IPC: G06F11/00 ,  G06F12/14 ,  G06F21/24 ,  G11C8/00

公开(公告)号：FR2349884A1

公开(公告)日：1977-11-25

申请号：FR7707755

申请日：1977-03-11

Applicant: IBM

Inventor： DAVIS MICHAEL I

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/18

公开(公告)号：FR2349883A1

公开(公告)日：1977-11-25

申请号：FR7707431

申请日：1977-03-04

Applicant: IBM

Inventor： BOURKE DONALL G ,  VERGARI LOUIS P ,  DAVIS MICHAEL I

IPC: G06F13/34 ,  G06F9/18 ,  G06F13/00

Abstract: The interface between I/O control logic, or channel, and peripheral devices permits simultaneous transfer of command, device address, and data. It includes logic in a peripheral device control unit, for dynamic change of the attached peripheral device interrupt priority level while the device may be executing a prior command. The I/O control logic includes means for initiating serial poll signalling while other transfers are taking place on the interface. Pref. this is achieved by utilizing the data transfer lines of the interface for data involved in the transfer, while utilizing a separate address bus for simultaneous transfer to a peripheral device control unit of a device address to be used for selection, and command information involved in the transfer.