公开(公告)号：CA1111924A

公开(公告)日：1981-11-03

申请号：CA277288

申请日：1977-04-29

Applicant: IBM

Inventor： BOUKNECHT MAX A ,  DAVIS MICHAEL I ,  VERGARI LOUIS P

IPC: G06F3/00 ,  G06F13/26 ,  G06F13/34 ,  G06F3/04 ,  G06F13/00

Abstract: INPUT/OUTPUT INTERFACE LOGIC FOR CONCURRENT OPERATIONS A data processing system with improved input/output (I/O) techniques is disclosed. The input/output control logic, or channel, of a central processing unit is connected to a plurality of peripheral input/output device control units, in parallel, by a plural line interface bus which includes bidirectional data transfer lines and bidirectional address transfer wires. The interface bus also includes unidirectional lines to and from peripheral device control units which synchronize operation of use of the bus. Several forms of I/O communications are shown to be controlled by the interface bus and include, direct processor controlled data transfer with simultaneous transmission of data and commands to peripheral devices, cycle steal data transfers permitting concurrent input/output operations and central processor program instruction execution, and peripheral device initated interrupt requests to the central processor. A common polling mechanism for selecting one of a plurality of peripheral devices which may be requesting cycle steal use of the bus or interrupt handling use of the bus is disclosed. During cycle steal data transfers, peripheral device status information can be transferred over the interface bus to the central processor storage without the need for requesting interrupt handling from the central processor.

公开(公告)号：CA1103325A

公开(公告)日：1981-06-16

申请号：CA277279

申请日：1977-04-29

Applicant: IBM

Inventor： BOURKE DONALL G ,  VERGARI LOUIS P

IPC: G06F13/10 ,  G06F13/34 ,  G06F3/00

Abstract: RESIDUAL STATUS REPORTING DURING CHAINED CYCLE STEAL INPUT/OUTPUT OPERATIONS A data processing system with improved input/output (I/O) techniques is disclosed. The input/output control logic, or channel, of a central processing unit is connected to a plurality of peripheral input/output device control units, in parallel, by a plural line interface bus which includes bidirectional data transfer lines and bidirectional address transfer wires. The interface bus also includes unidirectional lines to and from peripheral device control units which synchronize operation of use of the bus. Several forms of I/O communications are shown to be controlled by the interface bus and include, direct processor controlled data transfer with simultaneous transmission of data and commands to peripheral devices, cycle steal data transfers permitting concurrent input/output operations and central processor program instruction execution, and peripheral device initated interrupt requests to the central processor. A common polling mechanism for selecting one of a plurality of peripheral devices which may be requesting cycle steal use of the bus or interrupt handling use of the bus is disclosed. During cycle steal data transfers, peripheral device status information can be transferred over the interface bus to the central processor storage without the need for requesting interrupt handling from the central processor.

公开(公告)号：CA1092718A

公开(公告)日：1980-12-30

申请号：CA291144

申请日：1977-11-17

Applicant: IBM

Inventor： BOUKNECHT MAX A ,  VERGARI LOUIS P

IPC: G06F13/36 ,  G06F13/40 ,  G06F3/00

Abstract: INPUT/OUTPUT INTERFACE CONNECTOR CIRCUIT FOR REPOWERING AND ISOLATION In a data processing system which includes a base central processing unit, channel, and input/output (I/O) interface to which peripheral devices may be attached, a special attachment is disclosed. The attachment made to the base I/O interface includes connector circuitry which is required when the signals on the input/output interface must be repowered to peripheral devices in an expansion input/output unit, power isolation must be provided between a base data processing system and I/O expansion unit, or a remote peripheral device is to be attached to the base data processing system I/O interface. The connector circuit includes logic which responds to the normal I/O interface signals to energize drivers in the connector circuit to achieve repowering of signals on bidirectional signal lines and unidirectional signal lines.

公开(公告)号：FR2349883B1

公开(公告)日：1986-01-31

申请号：FR7707431

申请日：1977-03-04

Applicant: IBM

Inventor： BOURKE DONALL G ,  VERGARI LOUIS P ,  DAVIS MICHAEL I

IPC: G06F13/34 ,  G06F13/00

公开(公告)号：CA1103326A

公开(公告)日：1981-06-16

申请号：CA277289

申请日：1977-04-29

Applicant: IBM

Inventor： BOUKNECHT MAX A ,  BOURKE DONALL G ,  VERGARI LOUIS P

IPC: G06F13/12 ,  G06F9/46 ,  G06F13/34 ,  G06F3/04 ,  G06F13/00

Abstract: COMMON POLLING LOGIC FOR INPUT/OUTPUT INTERRUPT OR CYCLE STEAL DATA TRANSFER REQUESTS of The Disclosure A data processing system with improved input/output (I/O) techniques is disclosed. The input/output control logic, or channel, of a central processing unit is connected to a plurality of peripheral input/output device control units, in parallel, by a plural line interface bus which includes bidirectional data transfer lines and bidirectional address transfer wires. The interface bus also includes unidirectional lines to and from peripheral device control units which synchronize operation of use of the bus. Several forms of I/O communications are shown to be controlled by the interface bus and include, direct processor controlled data transfer with simultaneous transmission of data and commands to peripheral devices, cycle steal data transfers permitting concurrent input/output operations and central processor program instruction execution, and peripheral device initated interrupt requests to the central processor. A common polling mechanism for selecting one of a plurality of peripheral devices which may be requesting cycle steal use of the bus or interrupt handling use of the bus is disclosed. During cycle steal data transfers, peripheral device status information can be transferred over the interface bus to the central processor storage without the need for requesting interrupt handling from the central processor.

公开(公告)号：FR2349883A1

公开(公告)日：1977-11-25

申请号：FR7707431

申请日：1977-03-04

Applicant: IBM

Inventor： BOURKE DONALL G ,  VERGARI LOUIS P ,  DAVIS MICHAEL I

IPC: G06F13/34 ,  G06F9/18 ,  G06F13/00

Abstract: The interface between I/O control logic, or channel, and peripheral devices permits simultaneous transfer of command, device address, and data. It includes logic in a peripheral device control unit, for dynamic change of the attached peripheral device interrupt priority level while the device may be executing a prior command. The I/O control logic includes means for initiating serial poll signalling while other transfers are taking place on the interface. Pref. this is achieved by utilizing the data transfer lines of the interface for data involved in the transfer, while utilizing a separate address bus for simultaneous transfer to a peripheral device control unit of a device address to be used for selection, and command information involved in the transfer.